Contents
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Features
Logic Block Diagram1
CY14B108L, CY14B108N
Top View
Pinouts
12 Top View 13 not to scale
not to scale
CY14B108L, CY14B108N
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Table 1. Pin Definitions
SRAM Write
Device Operation
SRAM Read
AutoStore Operation
Software RECALL
Hardware RECALL Power Up
Software STORE
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CY14B108L, CY14B108N
Power
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Table 2. Mode Selection
Noise Considerations
Preventing AutoStore
Data Protection
Best Practices
Operating Range
DC Electrical Characteristics
Maximum Ratings
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Thermal Resistance
Data Retention and Endurance
Capacitance
AC Test Conditions
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AC Switching Characteristics
Switching Waveforms
CY14B108L, CY14B108N
Figure 6. SRAM Read Cycle #2 CE and OE Controlled3, 11
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CY14B108L, CY14B108N
Figure 7. SRAM Write Cycle #1 WE Controlled3, 14, 15
+ Feedback
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CY14B108L, CY14B108N
Controlled3, 14, 15
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AutoStore/Power Up RECALL
Switching Waveforms
CY14B108L, CY14B108N
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Software Controlled STORE/RECALL Cycle
Switching Waveforms
CY14B108L, CY14B108N
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Hardware STORE Cycle
Switching Waveforms
CY14B108L, CY14B108N
Truth Table For SRAM Operations
For x8 Configuration
For x16 Configuration
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Ordering Information
CY14B108L, CY14B108N
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Ordering Information continued
CY14B108L, CY14B108N
CY14B108L, CY14B108N
Part Numbering Nomenclature
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CY 14 B 108L-ZS P 20 X C T
CY14B108L, CY14B108N
Package Diagrams
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Figure 15. 44-Pin TSOP II
CY14B108L, CY14B108N
Package Diagrams continued
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Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
CY14B108L, CY14B108N
Package Diagrams continued
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Figure 17. 54-Pin TSOP II
CY14B108L, CY14B108N
Document History Page
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Document Title CY14B108L/CY14B108N 8 Mbit 1024K x 8/512K x 16 nvSRAM
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