Cypress manual Preliminary, CY14B108L, CY14B108N, + Feedback, Controlled3, 14, 15

PRELIMINARY		CY14B108L, CY14B108N
Figure 8. SRAM Write Cycle #2:
		Controlled[3, 14, 15, 16]
	CE

Address

CE

BHE, BLE

WE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled[3, 14, 15, 16]
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Document #: 001-45523 Rev. *B Page 12 of 24

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