Software Controlled STORE/RECALL Cycle | Cypress CY14B108N guide

PRELIMINARY	CY14B108L, CY14B108N

Software Controlled STORE/RECALL Cycle

In the following table, the software controlled STORE and RECALL cycle parameters are listed.[22, 23]

Parameters	Description		20 ns			25 ns			45 ns		Unit
Parameters	Description	Min		Max	Min		Max	Min		Max	Unit
		Min		Max	Min		Max	Min		Max
tRC	STORE/RECALL Initiation Cycle Time	20			25			45			ns
tSA	Address Setup Time	0			0			0			ns
tCW	Clock Pulse Width	15			20			30			ns
tHA	Address Hold Time	0			0			0			ns
tRECALL	RECALL Duration			200			200			200	μs

Switching Waveforms

Figure 11. CE and OE Controlled Software STORE/RECALL Cycle[23]

			tRC	tRC
	Address		Address #1	Address #6
		tSA	tCW	tCW
		tSA	tCW
	CE		tHA	tHA
	t		tHA
	t	SA	tHA		t
		SA

					HA
	OE
				tDELAY	tHHHD
	HSB (STORE only)	tLZCE	tHZCE		tLZHSB
		tLZCE			tLZHSB
	DQ (DATA)				High Impedance
	DQ (DATA)				tSTORE/tRECALL
					tSTORE/tRECALL
	RWI

Figure 12. Autostore Enable/Disable Cycle

	tRC
Address	Address #1
tSA	tCW
CE
tSA
OE
tLZCE
DQ (DATA)

		tRC
		Address #6
		tCW
	tHA	tHA
	tHA	tHA
	tHA	t
		HA
	tHZCE	tSS
	tHZCE	tDELAY
		tDELAY

Notes

22.The software sequence is clocked with CE controlled or OE controlled reads.

23.The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles.

Document #: 001-45523 Rev. *B

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Cypress CY14B108N, CY14B108L manual Software Controlled STORE/RECALL Cycle

Contents

Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor Corporation Not to scale PinoutsTop View Byte Low Enable, Active LOW . Controls DQ 7 DQ Output Enable, Active LOW . The active LO WByte High Enable, Active LOW . Controls DQ 15 DQ Power Supply Inputs to the Device Sram Write Device OperationSram Read AutoStore Operation Software Recall Hardware Recall Power UpSoftware Store Recall Mode SelectionStore Noise Considerations Preventing AutoStoreData Protection Best Practices Operating Range DC Electrical CharacteristicsMaximum Ratings Range Thermal Resistance Data Retention and EnduranceCapacitance AC Test Conditions Parameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write Cycle Sram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse Width High Z Inputs/Outputs Mode PowerTruth Table For Sram Operations CY14B108N-ZSP20XIT Ordering InformationCY14B108N-ZSP20XCT CY14B108N-ZSP25XCT CY14B108N-ZSP45XCT CY14B108N-ZSP45XIT ZS Tsop Part Numbering NomenclatureCY 14 B 108L-ZS P 20 X C T Nvsram Package Diagrams Pin Tsop II Ball Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Document HistoryGvch Sales, Solutions, and Legal Information USB