Package Diagrams, Pin Tsop II | Cypress CY14B108N, CY14B108L

PRELIMINARY	CY14B108L, CY14B108N

Package Diagrams

DIMENSION IN MM (INCH)

MAX

MIN.

O R E

K X A

S G

EJECTOR PIN

0° -5°

0.10 (.004)

18.517 (0.729)

18.313 (0.721)

10.262 (0.404)

10.058 (0.396)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

51-85087-*A

Document #: 001-45523 Rev. *B

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Contents

Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor Corporation Not to scale PinoutsTop View Output Enable, Active LOW . The active LO W Byte High Enable, Active LOW . Controls DQ 15 DQByte Low Enable, Active LOW . Controls DQ 7 DQ Power Supply Inputs to the Device Device Operation Sram ReadSram Write AutoStore Operation Software Recall Hardware Recall Power UpSoftware Store Recall Mode SelectionStore Preventing AutoStore Data ProtectionNoise Considerations Best Practices DC Electrical Characteristics Maximum RatingsOperating Range Range Data Retention and Endurance CapacitanceThermal Resistance AC Test Conditions AC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write Cycle Sram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse Width High Z Inputs/Outputs Mode PowerTruth Table For Sram Operations Ordering Information CY14B108N-ZSP20XCTCY14B108N-ZSP20XIT CY14B108N-ZSP25XCT CY14B108N-ZSP45XCT CY14B108N-ZSP45XIT Part Numbering Nomenclature CY 14 B 108L-ZS P 20 X C TZS Tsop Nvsram Package Diagrams Pin Tsop II Ball Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Document HistoryGvch Sales, Solutions, and Legal Information USB