Contents
Features
Logic Block Diagram1
PRELIMINARY
CY14B108L, CY14B108N
Pinouts
12 Top View 13 not to scale
Top View
not to scale
Table 1. Pin Definitions
PRELIMINARY
CY14B108L, CY14B108N
Device Operation
SRAM Read
SRAM Write
AutoStore Operation
Hardware RECALL Power Up
Software STORE
Software RECALL
PRELIMINARY
Power
PRELIMINARY
CY14B108L, CY14B108N
Table 2. Mode Selection
Preventing AutoStore
Data Protection
Noise Considerations
Best Practices
DC Electrical Characteristics
Maximum Ratings
Operating Range
PRELIMINARY
Data Retention and Endurance
Capacitance
Thermal Resistance
AC Test Conditions
AC Switching Characteristics
Switching Waveforms
PRELIMINARY
CY14B108L, CY14B108N
PRELIMINARY
CY14B108L, CY14B108N
Figure 6. SRAM Read Cycle #2 CE and OE Controlled3, 11
Figure 7. SRAM Write Cycle #1 WE Controlled3, 14, 15
PRELIMINARY
CY14B108L, CY14B108N
+ Feedback
Controlled3, 14, 15
AutoStore/Power Up RECALL
Switching Waveforms
PRELIMINARY
CY14B108L, CY14B108N
Software Controlled STORE/RECALL Cycle
Switching Waveforms
PRELIMINARY
CY14B108L, CY14B108N
Hardware STORE Cycle
Switching Waveforms
PRELIMINARY
CY14B108L, CY14B108N
For x8 Configuration
For x16 Configuration
Truth Table For SRAM Operations
PRELIMINARY
CY14B108L, CY14B108N
Ordering Information
PRELIMINARY
CY14B108L, CY14B108N
Ordering Information continued
PRELIMINARY
Part Numbering Nomenclature
PRELIMINARY
CY14B108L, CY14B108N
CY 14 B 108L-ZS P 20 X C T
Package Diagrams
PRELIMINARY
CY14B108L, CY14B108N
Figure 15. 44-Pin TSOP II
Package Diagrams continued
PRELIMINARY
CY14B108L, CY14B108N
Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
Package Diagrams continued
PRELIMINARY
CY14B108L, CY14B108N
Figure 17. 54-Pin TSOP II
Document History Page
PRELIMINARY
CY14B108L, CY14B108N
Document Title CY14B108L/CY14B108N 8 Mbit 1024K x 8/512K x 16 nvSRAM
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