Cypress CY7C1411JV18 manuals
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Cypress CY7C1411JV18 Manual
28 pages 693.11 Kb
36-Mbit QDR-II SRAM 4-Word Burst ArchitectureCY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18Features Configurations Functional Description Selection Guide 2 CY7C1411JV18, CY7C1426JV18Document Number: 001-12557 Rev. *C Page 2 of 28 Logic Block Diagram (CY7C1411JV18) Logic Block Diagram (CY7C1426JV18) 3 CY7C1413JV18, CY7C1415JV18Document Number: 001-12557 Rev. *C Page 3 of 28 Logic Block Diagram (CY7C1413JV18) Logic Block Diagram (CY7C1415JV18) 4 CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18Pin Configuration165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 5 CY7C1413JV18, CY7C1415JV18Pin Configuration165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 6 CY7C1411JV18, CY7C1426JV187 CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV188 CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18Functional OverviewRead Operations Write Operations Byte Write Operations Single Clock Mode Concurrent Transactions Depth Expansion Programmable Impedance Echo Clocks DLL 9 Application ExampleSRAM #4 SRAM #1 BUS MASTER (CPU or ASIC) 10 Truth TableWrite Cycle Descriptions 11 CY7C1411JV18, CY7C1426JV1812 IEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Test Data-Out (TDO) Performing a TAP Reset TAP Registers TAP Instruction Set 13 CY7C1413JV18, CY7C1415JV1814 CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18TAP Controller State Diagram 15 CY7C1413JV18, CY7C1415JV1818 CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18Boundary Scan Order Power Up Sequence in QDR-II SRAM 19 VVPower Up Sequence DLL Constraints / 26 CY7C1411JV18, CY7C1426JV18
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