Cypress CY7C1413JV18, CY7C1426JV18, CY7C1411JV18 Switching Characteristics, High, Low, DLL Timing

CY7C1411JV18, CY7C1426JV18

CY7C1413JV18, CY7C1415JV18

Switching Characteristics

Over the Operating Range [22]

Cypress

Consortium

Description

300 MHz

250 MHz

200 MHz

Unit

Parameter

Parameter

Min

Max

Min

Max

Min

Max

t

POWER

V (Typical) to the First Access [23]

1

1

1

ms

DD

tCYC

tKHKH

K Clock and C Clock Cycle Time

3.3

8.4

4.0

8.4

5.0

8.4

ns

tKH

tKHKL

1.32

–

1.6

–

2.0

–

ns

Input Clock (K/K;

C/C) HIGH

tKL

tKLKH

1.32

–

1.6

–

2.0

–

ns

Input Clock (K/K;

C/C) LOW

tKHKH

tKHKH

K Clock Rise to

Clock Rise and C to

Rise

1.49

–

1.8

–

2.2

–

ns

K

C

(rising edge to rising edge)

tKHCH

tKHCH

0

1.45

0

1.8

0

2.2

ns

K/K

Clock Rise to C/C Clock Rise (rising edge to rising edge)

Setup Times

tSA

tAVKH

Address Setup to K Clock Rise

0.4

–

0.5

–

0.6

–

ns

tSC

tIVKH

Control Setup to Clock (K,

0.4

–

0.5

–

0.6

–

ns

K) Rise (RPS, WPS)

tSCDDR

tIVKH

Double Data Rate Control Setup to Clock (K, K) Rise

0.3

–

0.35

–

0.4

–

ns

(BWS0, BWS1, BWS2, BWS3)

tSD

tDVKH

0.3

–

0.35

–

0.4

–

ns

D[X:0] Setup to Clock (K/K)

Rise

Hold Times

tHA

tKHAX

Address Hold after Clock (K/K

) Rise

0.4

–

0.5

–

0.6

–

ns

tHC

tKHIX

Control Hold after Clock (K /K) Rise

(RPS,

WPS)

0.4

–

0.5

–

0.6

–

ns

tHCDDR

tKHIX

Double Data Rate Control Hold after Clock (K/K)

Rise

0.3

–

0.35

–

0.4

–

ns

(BWS0, BWS1, BWS2, BWS3)

tHD

tKHDX

Rise

0.3

–

0.35

–

0.4

–

ns

D[X:0] Hold after Clock (K/K)

Output Times

tCO

tCHQV

C/C

Clock Rise (or K/K

in single clock mode) to Data Valid

–

0.45

–

0.45

–

0.45

ns

tDOH

tCHQX

Clock Rise

–0.45

–

–0.45

–

–0.45

–

ns

Data Output Hold after Output C/C

(Active to Active)

tCCQO

tCHCQV

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.45

ns

C/C

tCQOH

tCHCQX

Clock Rise

–0.45

–

–0.45

–

–0.45

–

ns

Echo Clock Hold after C/C

tCQD

tCQHQV

Echo Clock High to Data Valid

0.27

0.3

0.35

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.27

–

–0.3

–

–0.35

–

ns

t

CQH

t

Output Clock (CQ/CQ)

HIGH [24]

1.24

–

1.55

–

1.95

–

ns

CQHCQL

tCQHCQH

tCQHCQH

CQ Clock Rise to

CQ

Clock Rise

1.24

–

1.55

–

1.95

–

ns

(rising edge to rising edge) [24]

tCHZ

tCHQZ

Clock (C and

–

0.45

–

0.45

–

0.45

ns

C) Rise to High-Z (Active to High-Z) [25, 26]

tCLZ

tCHQX1

Clock (C and

–0.45

–

–0.45

–

–0.45

–

ns

C) Rise to Low-Z [25, 26]

DLL Timing

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

1024

–

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

30

30

ns

Notes

23.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be initiated.

24.These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) ia already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production

25.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.

26.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document Number: 001-12557 Rev. *C Page 23 of 28

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