Cypress CY7C1411JV18, CY7C1413JV18, CY7C1415JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18

CY7C1411JV18, CY7C1426JV18
CY7C1413JV18, CY7C1415JV18
Document Number: 001-12557 Rev. *C Page 3 of 28
Logic Block Diagram (CY7C1413JV18)
Logic Block Diagram (CY7C1415JV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
72
18
BWS[1:0]
VREF
Write Add. Decode
Write
Reg
36
A(18:0)
19
18
CQ
CQ
DOFF
Q[17:0]
18
18
18
Write
Reg Write Reg Write Reg
C
C
512K x 18 Array 512K x 18 Array 512K x 18 Array 512K x 18 Array
18
256K x 36 Array
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
18
144
36
BWS[3:0]
VREF
Write Add. Decode
Write
Reg
72
A(17:0)
18
256K x 36 Array 256K x 36 Array 256K x 36 Array
36
CQ
CQ
DOFF
Q[35:0]
36
36
36
Write
Reg Write Reg Write Reg
C
C
36
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