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Cypress CY7C1411JV18, CY7C1413JV18, CY7C1415JV18, CY7C1426JV18 CY7C1411JV18, CY7C1426JV18

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CY7C1411JV18, CY7C1426JV18

CY7C1413JV18, CY7C1415JV18

Document Number: 001-12557 Rev. *C Page 26 of 28

200 CY7C1411JV18-200BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1426JV18-200BZC

CY7C1413JV18-200BZC

CY7C1415JV18-200BZC

CY7C1411JV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1426JV18-200BZXC

CY7C1413JV18-200BZXC

CY7C1415JV18-200BZXC

CY7C1411JV18-200BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1426JV18-200BZI

CY7C1413JV18-200BZI

CY7C1415JV18-200BZI

CY7C1411JV18-200BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1426JV18-200BZXI

CY7C1413JV18-200BZXI

CY7C1415JV18-200BZXI

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

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Contents

Main 36-Mbit QDR-II SRAM 4-Word Burst Architecture CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Features Configurations Functional Description CY7C1411JV18, CY7C1426JV18 Document Number: 001-12557 Rev. *C Page 2 of 28 Logic Block Diagram (CY7C1411JV18) Logic Block Diagram (CY7C1426JV18) CY7C1413JV18, CY7C1415JV18 Document Number: 001-12557 Rev. *C Page 3 of 28 Logic Block Diagram (CY7C1413JV18) Logic Block Diagram (CY7C1415JV18) CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1413JV18, CY7C1415JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1411JV18, CY7C1426JV18 Pin Definitions CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 NC NC Pin Definitions CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example SRAM #4 SRAM #1 BUS MASTER (CPU or ASIC) Truth Table Write Cycle Descriptions CY7C1411JV18, CY7C1426JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) CY7C1413JV18, CY7C1415JV18 CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 TAP Controller State Diagram CY7C1413JV18, CY7C1415JV18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence DLL Constraints / Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Switching Waveforms READ READWRITE WRITE 12345 67 NOP NOP Ordering Information CY7C1411JV18, CY7C1426JV18 Ordering Information Document Number: 001-12557 Rev. *C Page 27 of 28 Package Diagram [+] Feedback Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm), 51-85195 51-85195-*A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page