Cypress CY7C1413JV18, CY7C1426JV18, CY7C1411JV18 Power Up Sequence in QDR-II Sram, DLL Constraints

CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18

Power Up Sequence in QDR-II SRAM

QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

❐Drive DOFF HIGH.

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency.

■Provide stable DOFF (HIGH), power and clock (K, K) for 1024 cycles to lock the DLL.

K

K

VDD/ VDDQ

DOFF

Figure 3. Power Up Waveforms

~ ~

	~ ~
Unstable Clock	> 1024 Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )

Fix High (or tie to VDDQ)

Document Number: 001-12557 Rev. *C Page 19 of 28

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