Cypress CY7C1510KV18 manuals
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Cypress CY7C1510KV18 Manual
30 pages 830.16 Kb
72-Mbit QDR-II SRAM 2-Word Burst ArchitectureCY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18Features Configurations Functional Description 2 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18Logic Block Diagram (CY7C1510KV18) Logic Block Diagram (CY7C1525KV18)Document Number: 001-00436 Rev. *E Page 3 of 30 3 Logic Block Diagram (CY7C1512KV18)Logic Block Diagram (CY7C1514KV18) 4 CY7C1512KV18, CY7C1514KV18Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 5 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV187 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV188 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18Functional OverviewRead Operations Write Operations Byte Write Operations Single Clock Mode Concurrent Transactions Depth Expansion Programmable Impedance Echo Clocks PLL 9 Application ExampleSRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) 10 CY7C1510KV18, CY7C1525KV18Truth Table Write Cycle Descriptions 12 CY7C1512KV18, CY7C1514KV18IEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In ( TDI) Test Data-Out (TDO) Performing a TAP Reset TAP Registers TAP Instruction Set 14 CY7C1512KV18, CY7C1514KV18TAP Controller State Diagram 15 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV1818 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18Boundary Scan Order Power Up Sequence in QDR-II SRAM 19 VVPower Up Sequence PLL Constraints / 25 CY7C1510KV18, CY7C1525KV18Switching WaveformsFigure 5. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 26 Ordering Information 29 Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180[+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) NOTES: PACKAGEWEIGHT : 0.475g JEDECREFERENCE : MO-216 / DESIGN 4.6C PACKAGECODE : BB0AC 30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page
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