Cypress CY7C1510KV18, CY7C1514KV18, CY7C1512KV18 manual Application Example, Echo Clocks, Sram #1

CY7C1510KV18, CY7C1525KV18

CY7C1512KV18, CY7C1514KV18

Echo Clocks PLL

Echo clocks are provided on the QDR-II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchro- nized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 23.

These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 μs of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 μs after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR-I mode (with one cycle latency and a longer access time).

Application Example
Figure 1 shows two QDR-II used in an application.
			Figure 1. Application Example
			SRAM #1		ZQ	R = 250ohms		SRAM #2		ZQ	R = 250ohms
	Vt		R W B		CQ/CQ#		R W B			CQ/CQ#
		D	P P W		Q	D	P	P W		Q
			S S S				S	S S
	R
		A	# # #	C C# K K#		A	# # #		C C# K K#
	DATA IN
	DATA OUT						Vt
	Address						Vt
BUS	RPS#						R
	WPS#
MASTER
	BWS#
(CPU
	CLKIN/CLKIN#
or	Source K
ASIC)
	Source K#
	Delayed K
	Delayed K#
	R	R = 50ohms	Vt = Vddq/2

Document Number: 001-00436 Rev. *E Page 9 of 30

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