CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Document Number: 001-00436 Rev. *E Page 23 of 30
Switching Characteristics Over the Operating Range [20, 21]
Cypress
Parameter
Consortium
Parameter Description
333 MHz 300 MHz 250 MHz 200 MHz 167 MHz
Unit
Min Max Min Max Min Max Min Max Min Max
tPOWER VDD(Typical) to the First Access [22] 11111ms
tCYC tKHKH K Clock and C Clock Cycle Time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
tKH tKHKL Input Clock (K/K; C/C) HIGH 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns
tKL tKLKH Input Clock (K/K; C/C) LOW 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns
tKHKHtKHKHK Clock Rise to K Clock Rise and C
to C Rise
(rising edge to rising edge)
1.35 – 1.49 – 1.8 – 2.2 – 2.7 – ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
01.3001.4501.802.202.7ns
Setup Times
tSA tAVKH Address Setup to K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tSC tIVKH Control Setup to K Clock Rise
(RPS, WPS)
0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tSCDDR tIVKH DDR Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
tSD tDVKH D[X:0] Setup to Clock (K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold Times
tHA tKHAX Address Hold after K Clock Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
tHC tKHIX Control Hold after K Clock Rise
(RPS, WPS)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
tHCDDR tKHIX DDR Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Notes
21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
operated and outputs data with the output timings of that frequency range.
22.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before initiating a read or write operation.
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