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Cypress CY7C1510KV18, CY7C1512KV18, CY7C1514KV18, CY7C1525KV18 - page 28

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CY7C1510KV18, CY7C1525KV18

CY7C1512KV18, CY7C1514KV18

Document Number: 001-00436 Rev. *E Page 28 of 30

167 CY7C1510KV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1525KV18-167BZC

CY7C1512KV18-167BZC

CY7C1514KV18-167BZC

CY7C1510KV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1525KV18-167BZXC

CY7C1512KV18-167BZXC

CY7C1514KV18-167BZXC

CY7C1510KV18-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1525KV18-167BZI

CY7C1512KV18-167BZI

CY7C1514KV18-167BZI

CY7C1510KV18-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1525KV18-167BZXI

CY7C1512KV18-167BZXI

CY7C1514KV18-167BZXI

Table 2. Ordering Information (continued)

Speed

(MHz) Ordering Code

Package

Diagram Package Type

Operating

Range

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Contents

Main 72-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Features Configurations Functional Description CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Logic Block Diagram (CY7C1510KV18) Logic Block Diagram (CY7C1525KV18) Document Number: 001-00436 Rev. *E Page 3 of 30 Logic Block Diagram (CY7C1512KV18) Logic Block Diagram (CY7C1514KV18) CY7C1512KV18, CY7C1514KV18 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Definitions CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 NC NC Pin Definitions CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example SRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) CY7C1510KV18, CY7C1525KV18 Truth Table Write Cycle Descriptions Page CY7C1512KV18, CY7C1514KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page CY7C1512KV18, CY7C1514KV18 TAP Controller State Diagram CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence PLL Constraints / Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics CY7C1510KV18, CY7C1525KV18 Switching Waveforms Figure 5. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 Ordering Information Page Page Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page