Epson RX-8801SA/JE manuals
Computer Equipment > Clock
When we buy new device such as Epson RX-8801SA/JE we often through away most of the documentation but the warranty.
Very often issues with Epson RX-8801SA/JE begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Clock Epson RX-8801SA/JE is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Clock on our side using links below.
Epson RX-8801SA/JE Manual
34 pages 517.83 Kb
2 NOTICE3 RX - 8801 SA / JEContents2. Block Diagram 3. Terminal description 4. Absolute Maximum Ratings 6. Frequency Characteristics 7. Electrical Characteristics 9. External Dimensions / Marking Layout 10. Application notes 4 I2C-BusInterface Real-timeClock Module1. Overview 2. Block Diagram 5 3. Terminal description6 4. Absolute Maximum RatingsItem Symbol Condition Rating Unit 5. Recommended Operating Conditions 7 7. Electrical Characteristics•Temperature compensation and consumption current 8 ProtocolSCL SDA 9 8. Use Methods10 8.2. Description of Registers 8.2.1. Register tableAddress Remark SEC MIN WEEK DAY MONTH YEAR RAM MIN Alarm HOUR Alarm WEEK Alarm DAY Alarm Extension Register USEL ∗1, ∗3, ∗5 Flag Register Control Register using the module time data is incorrect 11 8.2.2. Control register (Reg F)Control Register CSEL1 1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits CSEL0,1 CSEL0 Compensation interval (bit 7) (bit 6) 0.5 s Write/Read 2.0 s 10 s 30 s 2) UIE ( Update Interrupt Enable ) bit When a time update interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) When a time update interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) 2) TIE ( Timer Interrupt Enable ) bit When a fixed-cycletimer interrupt event occurs, an interrupt signal is not When a fixed-cycletimer interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) 12 3) AIE ( Alarm Interrupt Enable ) bitWhen an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) 4)RESET bit RESET Description [Normal operation mode] the fixed-cycletimer function [Operation stop mode] Stops updating of year, month, date, day, hour, minute, and second values and partially stops the fixed-cycletimer function (Stop 1) Stops updating of year, month, date, day, hour, minute, and second values • This stops all clock and calendar update operations Once this occurs, no more time update interrupt events or alarm interrupt events occur (Stop 2) Partially stops the fixed-cycletimer function • If the fixed-cycletimer's source clock settings include an update setting of 64 Hz, 1 Hz, or "Minute", the fixed-cycletimer function does not operate 13 Flag register1)UF ( Update Flag ) bit 2)TF ( Timer Flag ) bit 3)AF ( Alarm Flag ) bit 4)VLF ( Voltage Low Flag ) bit When after powering up from 0 V this bit's value is "1 VLF The VLF bit is cleared to zero to prepare for the next status detection Write This bit is invalid after a "1" has been written to it Data loss is not detected Read Data loss is detected. All registers must be initialized ( This setting is retained until a "zero" is written to this bit. ) 5) VDET ( Voltage Detection Flag ) bit VDET The VDET bit is cleared to zero to prepare for the next low voltage detection The write access of "1" to this bit is invalid Temperature compensation is normal Temperature compensation is stop detected 14 Extension RegisterUSEL TSEL1 1)TEST bit This is the manufacturer's test bit. Its value should always be "0 Be careful to avoid writing a "1" to this bit when writing to other bits TEST Normal operation mode 1Setting prohibited (manufacturer's test bit) 2)WADA ( Week Alarm/Day Alarm ) bit 3) USEL ( Update Interrupt Select ) bit update interrupts Auto reset time tRTN second update 500 ms minute update 7.813 ms 4) TE ( Timer Enable ) bit 5) FSEL0,1 ( FOUT frequency Select 0, 1 ) bits The combination of these two bits is used to set the FOUT frequency FSEL0,1 FOUT frequency (bit 3) (bit 2) 32768 Hz Output 1024 Hz Output 1 Hz Output 6) TSEL0,1 ( Timer Select 0, 1 ) bits TSEL0,1 Source clock (bit 1) (bit 0) /Once per 244.14 μs / Once per 15.625 ms "Second" update /Once per second "Minute" update /Once per minute 15 8.2.6. Clock counter (Reg - 0 ∼ 2)•The clock counter counts seconds, minutes, and hours The data format is BCD format 1) Second counter 00 seconds 2) Minute counter 00 minutes 3) Hour counter 00 hours •The day (of the week) is indicated by 7 bits, bit 0 to bit •The correspondence between days and count values is shown below Day Data [h] 01 h Monday 02 h 04 h 08 h 10 h Friday 20 h Saturday ∗ Do not set "1" to more than one day at the same time seven shown above should not be made as it may interfere with normal operation 16 MonthDate update pattern 1, 3, 5, 7, 8, 10, or 4, 6, 9, or February in normal year February in leap year 2) Month counter 01 (January) 3) Year counter Y80 Y40 Y20 Y10 • The year counter counts from 00, 01, 02 and up to 99, then starts again at When the value in the above 17 8.3. Fixed-cycleTimer Interrupt Function8.3.1. Diagram of fixed-cycletimer interrupt function TE bit TIE bit /INT output TF bit When a "1" is written to the TE bit, the When a (4)When the TF bit = "1" its value is retained until it is cleared to zero If the TIE bit = "1" when a If the TIE bit = "0" when a ∗/INT is again set low when the next interrupt event occurs When a "0" is written to the TE bit, the When /INT = low, the When /INT = low, the /INT pin status changes from low to 18 TSEL1TSEL0 Flag Register When the 1) TSEL0,1 bits (Timer Select 0, 1) TSEL0,1 Effects of tRTN RESET bits 4096 Hz /Once per 244.14 μs 122 μs 64 Hz 7.8125 ms countdown and interrupts is coordinated with the clock update timing 2) Fixed-cycleTimer Control register (Reg - B to C) Address C Address B 3) TE (Timer Enable) bit Data Stops fixed-cycletimer interrupt function Starts fixed-cycletimer interrupt function 4) TF (Timer Flag) bit The TF bit is cleared to zero to prepare for the next status detection Fixed-cycletimer interrupt events are not detected Fixed-cycletimer interrupt events are detected (Result is retained until this bit is cleared to zero.) 19 SCL pinSDA pin /INT pin 20 8.4. Time Update Interrupt Function21 ∗When the RESET bit value is "1" time update interrupt events do not occur1) USEL (Update Interrupt Select) bit Selects "second update" (once per second) as the timing for generation of interrupt events Selects "minute update" (once per minute) as the timing for generation of 2) UF (Update Flag) bit The UF bit is cleared to zero to prepare for the next status detection Time update interrupt events are not detected Time update interrupt events are detected (The result is retained until this bit is cleared to zero.) 3) UIE (Update Interrupt Enable) bit 1) Does not generate an interrupt signal when a time update interrupt event occurs (/INT remains Hi-Z) 2) Cancels interrupt signal triggered by time update interrupt event (/INT changes from low to Hi-Z) 22 8.5. Alarm Interrupt Function23 ∗When the RESET bit value is "1" alarm interrupt events do not occur1) WADA (Week Alarm /Day Alarm) bit WADA Sets WEEK as target of alarm function (DAY setting is ignored) Sets DAY as target of alarm function (WEEK setting is ignored) 2) Alarm registers (Reg - 8 to A) ∗1) The register that "1" was set to "AE" bit, doesn't compare alarm (Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - A): As a result, alarm occurs if only an hour and minute accords with alarm data 24 3) AF (Alarm Flag) bitThe AF bit is cleared to zero to prepare for the next status detection Alarm interrupt events are not detected Alarm interrupt events are detected 4) AIE (Alarm Interrupt Enable) bit 1) When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status remains Hi-Z) 2) When an alarm interrupt event occurs, the interrupt signal is canceled (/INT status changes from low to Hi-Z) 8.5.2.Examples of alarm settings 1)Example of alarm settings when "Day" has been specified (and WADA bit = "0") Day is specified Reg – A Reg WADA bit = "0 S F T W T M S Alarm Monday through Friday, at 7:00 AM 07 h 80 h ∼ FF h ∗ Minute value is ignored Every Saturday and Sunday, for 30 minutes 30 h each hour ∗ Hour value is ignored Every day, at 6:59 AM 18 h 59 h Χ: Don't care 2) Example of alarm settings when "Day" has been specified (and WADA bit = "1") Reg - A Reg WADA bit = "1 First of each month, at 7:00 AM 15th of each month, for 30 minutes each hour ∗ Hour value is ignored Every day, at 6:59 PM 25 8.6. Reading/Writing Data via the I2C Bus Interface26 0.95 s ( Max. )1) START condition, repeated START condition, and STOP condition (1)START condition The SDA level changes from high to low while SCL is at high level (2)STOP condition (3)Repeated START condition (RESTART condition) 2)Caution points within 0.95 seconds 0.95 seconds or longer Restarting of communications begins with transfer of the START condition again at least 1.3 μs (see the tBUF rule) 61 μs (Min.) 27 However, the transfer time must be no longer than 0.95 secondsAfter address Fh, incrementation goes to address 0h [0110 65 h 64 h 29 Unit30 I2C-BUSMaster RX-8801 31 9. External Dimensions / Marking Layout9.1. RX − 8801 SA ( SOP − 14pin ) ( SOP 14pin ) 9.1.1. External dimensions RX − 8801 SA ( SOP − 14pin ) 10.1 ± 0° - 10° 5.0 7.4 ± Min Unit : mm 9.1.2. Marking layout Type Logo Production lot 32 9.2.RX − 8801 JE ( VSOJ − 20pin )9.2.1. External dimensions RX − 8801 JE ( VSOJ − 20pin ) • External dimensions • Recommended soldering pattern (0.75) 6.0 ± ⋅ 9 1.5 Max 0.65 0 Min 9.2.2. Marking layout 33 10.Application notes1)Notes on handling 2) Notes on packaging AMERICA EUROPE ASIA 34 DistributorElectronic devices information on WWW server http://www.epsontoyocom.co.jp
Also you can find more Epson manuals or manuals for other Computer Equipment.