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Epson RX-8801SA/JE bit, bit, bit, bit, bit, bit, bit, bit, SEC, MIN, DAY, RAM, VLF, UIE, TIE, AIE, HOUR, WEEK, YEAR, TEST, WADA, USEL, VDET, Page, MONTH, FSEL1, FSEL0, TSEL1

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RX − 8801 SA / JE

8.2. Description of Registers 8.2.1. Register table

Address		Function	bit 7			bit 6			bit 5			bit 4		bit 3			bit 2			bit 1			bit 0	Remark

0		SEC	{		40			20			10			8		4			2			1			∗
0		SEC			40			20			10			8		4			2			1			3
1		MIN	{			40			20			10		8			4			2			1		∗
1		MIN				40			20			10		8			4			2			1		3

2		HOUR	{			{			20			10		8			4			2			1		∗
2		HOUR							20			10		8			4			2			1		3

3		WEEK	{			6			5			4		3			2			1			0		∗
3		WEEK				6			5			4		3			2			1			0		3

4		DAY	{			{			20			10		8			4			2			1		∗
4		DAY							20			10		8			4			2			1		3

5		MONTH										10		8			4			2			1		3
			{			{			{																∗

6		YEAR	80			40			20			10		8			4			2			1		−

7		RAM	•			•			•			•		•			•			•			•		∗4

8		MIN Alarm	AE			40			20			10		8			4			2			1		−

9		HOUR Alarm	AE			•			20			10		8			4			2			1		∗4

A		WEEK Alarm	AE			6			5			4		3			2			1			0		∗4

		DAY Alarm							20			10		8			4			2			1
		DAY Alarm				•			20			10		8			4			2			1

B		Timer Counter 0	128			64			32			16		8			4			2			1		−

C		Timer Counter 1	•			•			•			•		2048			1024			512			256		∗4

D		Extension Register	TEST			WADA			USEL			TE		FSEL1			FSEL0			TSEL1			TSEL0	∗1, ∗3, ∗5

E		Flag Register	{			{			UF			TF		AF			{			VLF			VDET	∗	∗	∗
E		Flag Register							UF			TF		AF						VLF			VDET	1,	2,	3

F		Control Register	CSEL1			CSEL0			UIE			TIE		AIE			{			{			RESET		∗
F		Control Register	CSEL1			CSEL0			UIE			TIE		AIE									RESET		3

Note	When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before
	using the module.
	Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
	time data is incorrect.

∗1) During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".

∗At this point, all other register values are undefined, so be sure to perform a reset before using the module. ∗2) Only a "0" can be written to the UF, TF, AF, or VLF bit.

∗3) Any bit marked with "{" should be used with a value of "0" after initialization.

∗4) Any bit marked with "•" is a RAM bit that can be used to read or write any data.

∗5) The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.

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ETM26E-03

Contents

Page NOTICE RX - 8801 SA / JE Contents 2. Block Diagram 3. Terminal description 4. Absolute Maximum Ratings I2C-BusInterface Real-timeClock Module 1. Overview 2. Block Diagram 3. Terminal description RX − 8801 SA RX − 8801 JE 4. Absolute Maximum Ratings Item Symbol Condition Rating 7. Electrical Characteristics •Temperature compensation and consumption current Protocol SCL SDA 8. Use Methods 8.2. Description of Registers 8.2.1. Register table Address Remark SEC MIN 8.2.2. Control register (Reg F) Control Register CSEL1 1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits CSEL0,1 3) AIE ( Alarm Interrupt Enable ) bit When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) Flag register 1)UF ( Update Flag ) bit 2)TF ( Timer Flag ) bit 3)AF ( Alarm Flag ) bit 4)VLF ( Voltage Low Flag ) bit Extension Register USEL TSEL1 1)TEST bit This is the manufacturer's test bit. Its value should always be "0 8.2.6. Clock counter (Reg - 0 ∼ 2) •The clock counter counts seconds, minutes, and hours The data format is BCD format 1) Second counter 00 seconds Month Date update pattern 1, 3, 5, 7, 8, 10, or 4, 6, 9, or February in normal year 8.3. Fixed-cycleTimer Interrupt Function 8.3.1. Diagram of fixed-cycletimer interrupt function TE bit TIE bit /INT output TSEL1 TSEL0 Flag Register When the 1) TSEL0,1 bits (Timer Select 0, 1) SCL pin SDA pin /INT pin 8.4. Time Update Interrupt Function ∗When the RESET bit value is "1" time update interrupt events do not occur 1) USEL (Update Interrupt Select) bit Selects "second update" (once per second) as the timing for generation of interrupt events Selects "minute update" (once per minute) as the timing for generation of 8.5. Alarm Interrupt Function ∗When the RESET bit value is "1" alarm interrupt events do not occur 1) WADA (Week Alarm /Day Alarm) bit WADA Sets WEEK as target of alarm function (DAY setting is ignored) 3) AF (Alarm Flag) bit The AF bit is cleared to zero to prepare for the next status detection Alarm interrupt events are not detected Alarm interrupt events are detected 4) AIE (Alarm Interrupt Enable) bit 8.6. Reading/Writing Data via the I2C Bus Interface 0.95 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1)START condition The SDA level changes from high to low while SCL is at high level (2)STOP condition However, the transfer time must be no longer than 0.95 seconds After address Fh, incrementation goes to address 0h [0110 65 h 64 h Page Unit I2C-BUS Master RX-8801 9. External Dimensions / Marking Layout 9.1. RX − 8801 SA ( SOP − 14pin ) ( SOP 14pin ) 9.1.1. External dimensions 9.2.RX − 8801 JE ( VSOJ − 20pin ) 9.2.1. External dimensions RX − 8801 JE ( VSOJ − 20pin ) • External dimensions • Recommended soldering pattern 10.Application notes 1)Notes on handling 2) Notes on packaging AMERICA EUROPE Distributor Electronic devices information on WWW server http://www.epsontoyocom.co.jp