RX − 8801 SA / JE
3) AIE ( Alarm Interrupt Enable ) bitWhen an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.
AIE | Data | Function |
| 0 | When an alarm interrupt event occurs, an interrupt signal is not generated |
| or is canceled (/INT status changes from low to | |
|
| |
|
|
|
Write/Read |
| When an alarm interrupt event occurs, an interrupt signal is generated (/INT |
| status changes from | |
| 1 | |
| ∗ When an alarm interrupt event has been generated | |
|
| only when the value of the control register's AIE bit is "1". This setting is retained until the AF |
|
| bit value is cleared to zero. (No automatic cancellation) |
|
|
|
∗For details, see "8.5. Alarm Interrupt Function".
[Caution]
(1)The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.
When an interrupt has occurred (when the /INT pin is at low level), the UF, TF, read AF flags to determine which flag has a value of "1" (this indicates which type of interrupt event has occurred).
(2)To keep the /INT pin from changing to low level, write "0" to the UIE, TIE, and AIE bits. To check whether an event has occurred without outputting any interrupts via the /INT pin, use software to monitor the value of the UF, TF, and AF interrupt flags.
4)RESET bitIt also resets the RTC module's internal counter value when the value is less than one second.
Writing a "1" to this bit stops the counter operation and resets the RTC module's internal counter value when the value is less than one second.
If a
∗For optimum performance, do not use this bit for functions other than the clock and calendar functions.
RESET | Data | Description |
|
| [Normal operation mode] |
|
| This bit is used to cancel stop status for (i.e., restart) the clock and calendar |
| 0 | function. Also, when "1" is written to the RESET bit, it cancels stop status for |
|
| the |
|
| ∗ Since operation is not restarted when the STOP bit value is "1", to restart operation, a "0" must |
|
| be written to both the STOP bit and the RESET bit. |
|
| [Operation stop mode] |
|
| Stops updating of year, month, date, day, hour, minute, and second values |
|
| and partially stops the |
Write/Read |
| (Stop 1) Stops updating of year, month, date, day, hour, minute, and |
| second values | |
|
| • This stops all clock and calendar update operations. |
|
| Once this occurs, no more time update interrupt events or alarm |
| 1 | interrupt events occur. |
|
| |
|
| (Stop 2) Partially stops the |
|
| • If the |
|
| setting of 64 Hz, 1 Hz, or "Minute", the |
|
| not operate. |
|
| ∗ However, this function does operate when the |
|
| 4096 Hz. |
|
| (Note) When this bit value is "1", the internal divider keeps the reset state, from 2048Hz to 1 |
|
| Hz . |
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