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Epson RX-8801SA/JE I2C-BusInterface Real-timeClock Module, 1. Overview, 2. Block Diagram, RX − 8801 SA / JE, Page, ETM26E-03

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RX − 8801 SA / JE

I2C-Bus Interface Real-time Clock Module

RX − 8801 SA / JE

•Features built-in 32.768 kHz DTCXO, High Stability.

•Supports I2C-Bus's high speed mode (400 kHz)

•Alarm interrupt function for day, date, hour, and minute settings

•Fixed-cycle timer interrupt function

• Time update interrupt function		(Seconds, minutes)
•	32.768 kHz output with OE function	(FOE and FOUT pins)
•	Auto correction of leap years	(from 2000 to 2099)

•Wide interface voltage range: 2.2 V to 5.5 V

•Wide time-keeping voltage range:1.6 V to 5.5 V

•Low current consumption: 0.8μA / 3 V (Typ.)

The I2C-BUS is a trademark of NXP Semiconductors.

1. Overview

This module is an I2C bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO.

In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer function, time update interrupt function, and 32.768 kHz output function.

The devices in this module are fabricated via a C-MOS process for low current consumption, which enables long-term battery back-up.

All of these many functions are implemented in SOP-14 pin and VSOJ-20 pin package.

2. Block Diagram

32.768 kHz

32kHz

DTCXO

						CLOCK
DIVIDER						and
DIVIDER						and
						CALENDAR
						CALENDAR

FOUT				FOUT							TIMER
FOUT

FOE				CONTROLLER							REGISTER
FOE


/ INT				INTERRUPT							ALARM
				INTERRUPT							ALARM
				CONTROLLER							REGISTER
				CONTROLLER							REGISTER


											CONTROL
SCL				I2C-BUS							REGISTER
				INTERFACE							and
				INTERFACE							and
SDA				CIRCUIT							SYSTEM
SDA											SYSTEM
											CONTROLLER

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ETM26E-03

Contents

Page NOTICE RX - 8801 SA / JE Contents 2. Block Diagram 3. Terminal description 4. Absolute Maximum Ratings I2C-BusInterface Real-timeClock Module 1. Overview 2. Block Diagram 3. Terminal description RX − 8801 SA RX − 8801 JE 4. Absolute Maximum Ratings Item Symbol Condition Rating 7. Electrical Characteristics •Temperature compensation and consumption current Protocol SCL SDA 8. Use Methods 8.2. Description of Registers 8.2.1. Register table Address Remark SEC MIN 8.2.2. Control register (Reg F) Control Register CSEL1 1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits CSEL0,1 3) AIE ( Alarm Interrupt Enable ) bit When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) Flag register 1)UF ( Update Flag ) bit 2)TF ( Timer Flag ) bit 3)AF ( Alarm Flag ) bit 4)VLF ( Voltage Low Flag ) bit Extension Register USEL TSEL1 1)TEST bit This is the manufacturer's test bit. Its value should always be "0 8.2.6. Clock counter (Reg - 0 ∼ 2) •The clock counter counts seconds, minutes, and hours The data format is BCD format 1) Second counter 00 seconds Month Date update pattern 1, 3, 5, 7, 8, 10, or 4, 6, 9, or February in normal year 8.3. Fixed-cycleTimer Interrupt Function 8.3.1. Diagram of fixed-cycletimer interrupt function TE bit TIE bit /INT output TSEL1 TSEL0 Flag Register When the 1) TSEL0,1 bits (Timer Select 0, 1) SCL pin SDA pin /INT pin 8.4. Time Update Interrupt Function ∗When the RESET bit value is "1" time update interrupt events do not occur 1) USEL (Update Interrupt Select) bit Selects "second update" (once per second) as the timing for generation of interrupt events Selects "minute update" (once per minute) as the timing for generation of 8.5. Alarm Interrupt Function ∗When the RESET bit value is "1" alarm interrupt events do not occur 1) WADA (Week Alarm /Day Alarm) bit WADA Sets WEEK as target of alarm function (DAY setting is ignored) 3) AF (Alarm Flag) bit The AF bit is cleared to zero to prepare for the next status detection Alarm interrupt events are not detected Alarm interrupt events are detected 4) AIE (Alarm Interrupt Enable) bit 8.6. Reading/Writing Data via the I2C Bus Interface 0.95 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1)START condition The SDA level changes from high to low while SCL is at high level (2)STOP condition However, the transfer time must be no longer than 0.95 seconds After address Fh, incrementation goes to address 0h [0110 65 h 64 h Page Unit I2C-BUS Master RX-8801 9. External Dimensions / Marking Layout 9.1. RX − 8801 SA ( SOP − 14pin ) ( SOP 14pin ) 9.1.1. External dimensions 9.2.RX − 8801 JE ( VSOJ − 20pin ) 9.2.1. External dimensions RX − 8801 JE ( VSOJ − 20pin ) • External dimensions • Recommended soldering pattern 10.Application notes 1)Notes on handling 2) Notes on packaging AMERICA EUROPE Distributor Electronic devices information on WWW server http://www.epsontoyocom.co.jp