Manuals / Brands / Computer Equipment / Clock / Epson / Computer Equipment / Clock

Epson RX-8801SA/JE Protocol, SCL, SDA, Min, Typ, Max, Item, Unit, Page, Symbol, Condition, ETM26E-03, 0.95 seconds, 7.2. AC Characteristics

1 34

Download 34 pages, 517.83 Kb

RX − 8801 SA / JE

7.2. AC Characteristics

* Unless otherwise specified,

GND = 0 V , VDD

= 1.8 V to 5.5 V , Ta = −40 °C to +85 °C

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

SCL clock frequency

fSCL

400

kHz

Start condition setup time

tSU;STA

0.6

μs

Start condition hold time

tHD;STA

0.6

μs

Data setup time

tSU;DAT

100

ns

Data hold time

tHD;DAT

0

900

ns

Stop condition setup time

tSU;STO

0.6

μs

Bus idle time between

tBUF

1.3

μs

start condition and stop condition

Time when SCL = "L"

tLOW

1.3

μs

Time when SCL = "H"

tHIGH

0.6

μs

Rise time for SCL and SDA

tr

0.3

μs

Fall time for SCL and SDA

tf

0.3

μs

Allowable spike time on bus

tSP

50

ns

FOUT duty

tW /t

50% of VDD level

40

50

60

%

Timing chart

Protocol

START

BIT 7

BIT 6

BIT 0

ACK

STOP

START

CONDITION

MSB

(A6)

LSB

(A)

CONDITION

CONDITION

(S)

(A7)

(R/W)

(P)

(S)

tSU ; STA

tLOW

tHIGH

1 / fSCL

tSU ; STA

SCL

(P)

(S)

(S)

tBUF

tr

tf

SDA

(A)

tHD ; STA

tSU ; DAT

tHD ; DAT

tSP

tSU ; STO

tHD ; STA

Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop condition after access should be completed within 0.95 seconds.

If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus timeout function.

Page - 5

ETM26E-03

Contents

Page NOTICE RX - 8801 SA / JE Contents 2. Block Diagram 3. Terminal description 4. Absolute Maximum Ratings I2C-BusInterface Real-timeClock Module 1. Overview 2. Block Diagram 3. Terminal description RX − 8801 SA RX − 8801 JE 4. Absolute Maximum Ratings Item Symbol Condition Rating 7. Electrical Characteristics •Temperature compensation and consumption current Protocol SCL SDA 8. Use Methods 8.2. Description of Registers 8.2.1. Register table Address Remark SEC MIN 8.2.2. Control register (Reg F) Control Register CSEL1 1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits CSEL0,1 3) AIE ( Alarm Interrupt Enable ) bit When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) Flag register 1)UF ( Update Flag ) bit 2)TF ( Timer Flag ) bit 3)AF ( Alarm Flag ) bit 4)VLF ( Voltage Low Flag ) bit Extension Register USEL TSEL1 1)TEST bit This is the manufacturer's test bit. Its value should always be "0 8.2.6. Clock counter (Reg - 0 ∼ 2) •The clock counter counts seconds, minutes, and hours The data format is BCD format 1) Second counter 00 seconds Month Date update pattern 1, 3, 5, 7, 8, 10, or 4, 6, 9, or February in normal year 8.3. Fixed-cycleTimer Interrupt Function 8.3.1. Diagram of fixed-cycletimer interrupt function TE bit TIE bit /INT output TSEL1 TSEL0 Flag Register When the 1) TSEL0,1 bits (Timer Select 0, 1) SCL pin SDA pin /INT pin 8.4. Time Update Interrupt Function ∗When the RESET bit value is "1" time update interrupt events do not occur 1) USEL (Update Interrupt Select) bit Selects "second update" (once per second) as the timing for generation of interrupt events Selects "minute update" (once per minute) as the timing for generation of 8.5. Alarm Interrupt Function ∗When the RESET bit value is "1" alarm interrupt events do not occur 1) WADA (Week Alarm /Day Alarm) bit WADA Sets WEEK as target of alarm function (DAY setting is ignored) 3) AF (Alarm Flag) bit The AF bit is cleared to zero to prepare for the next status detection Alarm interrupt events are not detected Alarm interrupt events are detected 4) AIE (Alarm Interrupt Enable) bit 8.6. Reading/Writing Data via the I2C Bus Interface 0.95 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1)START condition The SDA level changes from high to low while SCL is at high level (2)STOP condition However, the transfer time must be no longer than 0.95 seconds After address Fh, incrementation goes to address 0h [0110 65 h 64 h Page Unit I2C-BUS Master RX-8801 9. External Dimensions / Marking Layout 9.1. RX − 8801 SA ( SOP − 14pin ) ( SOP 14pin ) 9.1.1. External dimensions 9.2.RX − 8801 JE ( VSOJ − 20pin ) 9.2.1. External dimensions RX − 8801 JE ( VSOJ − 20pin ) • External dimensions • Recommended soldering pattern 10.Application notes 1)Notes on handling 2) Notes on packaging AMERICA EUROPE Distributor Electronic devices information on WWW server http://www.epsontoyocom.co.jp