Fujitsu FR60 manuals
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1038 pages 10.51 Mb
4 -i2004 FUJITSU LIMITED Printed in Japan 5 TOC229 230 231 7. Caution233 Chapter 15 CAN Clock Prescaler237 Chapter 16 Clock Supervisor222Chapter 16 Clock Supervisor 2.Clock Supervisor Register 0004ADSSVE SRST MSVE MM SM RCE SCKS OUTE 0 0 0 1 1 1 0 0 R/W 238 Clock Supervisor Control Register (CSVCR)76543210 R/W R R R/W R/W R/W R/W Initial Value 224Chapter 16 Clock Supervisor 3.Block Diagram Clock Supervisor Block Diagram Clock SupervisorFigure 3-1 Bock Diagram Clock Supervisor Internal Bus 240 Clock Supervisor811 L H L L H H L H H L L H L H L H Chapter 39 Programmable Pulse Generator 813 PPG (0-3)Selector PCSR PDUT PTMRSelector PPG2/3 interrupt (#114/#115) PPG0/P17.0 PPG1/P17.1 PPG2/P17.2 PPG3/P17.3 PPG0/1 interrupt (#112/#113) 815 4.1 PCSR: PPG Cycle Setting Register816 4.2 PDUT: PPG Duty Setting Register817 4.3 PCN: PPG Control Status register820 4.4 GCN1: General Control register 1822 4.5 GCN2: General Control Register 2823 4.6 PTMR: PPG Timer Register808 (See 8. Caution (Page No.821).) 824 5.1 PWM OperationIn PWM operation, variable-duty pulses are generated from the PPG pin. 809 Equation 825 5.2 One-Shot OperationIn one-shot operation, one-shot pulses are generated from the PPG pin. 826 5.3 Restart Operation829 7.1 How do I set (rewrite) a cycle and a duty?7.2 How do I enable or disable PPG operations? 7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)? 7.4 How do I get it restarted? 830 7.5 What count clocks are available and how are they selected?7.6 How do I clamp the PPG pin output level? 831 7.7 What activation triggers are available and how are they selected?832 816Triggers are selectable for PPG8, PPG9, PPG10, and PPG11 independently. Triggers are selectable for PPG12, PPG13, PPG14, and PPG15 independently. 833 7.8 How do I invert the output polarity?7.9 How do I program a pin as a PPG output pin? 834 7.10 How do I generate an activation trigger?7.11 How do I stop a PPG operation? 7.12 What interrupt registers are used? 836 7.13 What interrupts are available and how are they selected?7.14 How do I enable, disable and clear interrupts? 839 Chapter 40 Pulse Frequency Modulator851 Chapter 41 Up/Down Counter879 Chapter 42 Sound Generator887 Chapter 43 Stepper Motor ControllerSMC channel 0 (ADC input) Remark: The SMC channels 0, 1, 2 and 3 are shared with ADC inputs.Block Diagram of Stepping Motor ControllerFigure 1-1 Stepping Motor Controller with A/D Converter Function 872 Figure 1-2 Stepping Motor Controller 888 Remark: The SMC channels 4 and 5 are not shared with ADC inputs. 2. RegistersCK EN PWM PWM2PCK EN PWM Peripheral clock CLKP 889 2.1 Registers for Stepping Motor Controller890 PWM Control RegisterP2 0x0C1, 0x0C3 0x0C5, 0x0C7 0x0C9, 0x0CB 892 PWM1&2 Compare Registers893 877Figure 2-1 Relationship between the Compare Register Setting Value and PWM Pulse Width 894 PWM1&2 Selection Registers0x096, 0x09E 0x0A6, 0x0AE 0x0B6, 0x0BE 0x097, 0x09F 0x0A7, 0x0AF 0x0B7, 0x0BF895 8792.RegistersWhen set a BS bit in "0" before the PWM cycle end Load Not load XXXhWhen set a BS bit in "0" with automatic clear simultaneously Figure 2-2 load timing of PWM compare register valueWhen set a BS bit in "1" with automatic clear simultaneously [Automatic clear of BS bit] 881 897 3. Operation The operation of the stepping motor controller is explained.901 Chapter 44 A/D Converter1. Overview of A/D ConverterInput impedance886Chapter 44 A/D Converter 2.Block Diagram of A/D Converter Figure 2-1 Figure 20.2-1 "Block Diagram of A/D Converter" 902 2. Block Diagram of A/D ConverterFollowing figure shows block diagram of A/D converter. Block diagram of A/D converter input circ u it Sample &Hold circuit Comparator Decoder Dat a bus 903 3. Registers of A/D ConverterRegister list904 888 ADCS0 (ADC0): Address 01A5h (Access: Half-word, Byte) ADCR1 (ADC0): Address 01A6h (Access: Word, Half-word, Byte) ADCR0 (ADC0): Address 01A7h (Access: Word, Half-word, Byte) ADCT1 (ADC0): Address 01A8h (Access: Word, Half-word, Byte) ADCT0 (ADC0): Address 01A9h (Access: Word, Half-word, Byte) ADSCH (ADC0): Address 01AAh (Access: Word, Half-word, Byte) 889 ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte) 905 3.1 A/D Enable Register (ADER)While a pin is used as analog input, corresponding bit in ADER register have to be set to 1. A/D enable register (ADER) ADERH (ADC0): Address 01A0h (Access: Word, Half-word, Byte) ADERL (ADC0): Address 01A2h (Access: Word, Half-word, Byte) [ADE31-0]: A/D Input Enable RST clears them to 0. Be sure to set start channel and end channel to 1. 906 3.2 A/D Control Status Register (ADCS)908 3.3 Data Register (ADCR1, ADCR0)Data register (ADCR1, ADCR0) 909 3.4 Sampling Timer Setting Register (ADCT)Sampling timer setting register (ADCT) 910 3.5 A/D Channel Setting Register (ADSCH, ADECH)A/D channel setting register (ADSCH, ADECH) 912 4. Operation of A/D ConverterSingle Mode Continuous Mode Stop Mode 913 4.1 Single-shot conversion mode914 4.2 Scan conversion mode915 5. SettingTable 5-1 Settings needed to use A/D - Single-Shot Conversion Mode Table 5-2 Settings needed to use A/D - Scan Conversion Mode 918 6.3 How do I set a conversion time?6.4 How do I enable analog pin input? 919 6.5 How do I enable analog pin input for Stepper Motor Controller?6.6 To select how to activate the A/D converter 920 6.7 To activate the A/D converter6.8 To verify the end of a conversion 6.9 How do I read a conversion value? 6.10 How do I force an A/D conversion operation to a stop? 921 6.11 What interrupt registers are used?6.12 What interrupts are available? 6.13 How do I enable, disable, clear interrupts? 922 7. Caution925 Chapter 45 D/A Converter910Chapter 45 D/A Converter AVcc AVss For a detailed description of the D/A pin circuit, see the chapter entitled Basic Information. 926 D/A converter (0-1)DA0/P28.6 DA1/P28.7 DADR0/ DADR1 1 0From Port Data register Port read Register number (:bit) 927 4.1 DADR: D/A Data Register4.2 DACR: D/A Control Register 932 8. Caution The table below lists the output voltages of the D/A converter (in 10-bit resolution mode). The table below lists the output voltages of the D/A converte (in 8-bit resolution mode)r. 917Chapter 46 Alarm Comparator 933 ACSR
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