Interphase Tech 4538 manuals

149 pages1.21 Mb

3Copyright Notice
Disclaimer
Trademark Acknowledgments
4Assistance
Product Purchased from Reseller
Product Purchased Directly from Interphase Corporation
5END-USERLICENSE AGREEMENT
FOR INTERPHASE CORPORATION SOFTWARE
IMPORTANT NOTICE TO USER–READCAREFULLY
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Restrictions on Use:
Ownership of Software:
Software Transfer:
Limited Warranty:
6Limitation of Liability:
Confidentiality:
Termination:
Export:
U.S. Government Restricted Rights:
General:
7Contents
- 8CHAPTER 2 4538 Power-UpInitialization
- 9CHAPTER 3 Programming the Peripherals
- CHAPTER 4 Accessing the 4538 on the PCI Side
- 10CHAPTER 5 Connectors and Front Panel
- APPENDIX A Mechanical Information
11List of Figures
13List of Tables
15List of Examples
17Using This Guide
- 18NOTE
- 19CAUTION
- WARNING
- Return
- 20WWWMethod
- FTP Method
- 21<directory
231Hardware Description
- 244538 Hardware Structure
- Figure 1-1.4538 Structure
- 25PowerQUICC II Resets
- 26System Clocks
- PCI Local Space Mapping
- 27Table 1-1.PCI Local Space Mapping
- 28Figure 1-2.Local Space Mapping
- 29Interrupts
- Table 1-2.Local Interrupts
- Table 1-3.PowerQUICC II Memory Controller Machine Usage
- 30Communication Processor Module (CPM) I/O Ports
- 7DEOHCPM Port A Usage
- 'LU
- 7DEOHCPM Port B Usage
- 317DEOHCPM Port C Usage
- Table 1-7.CPM Port D Usage
- 32Table 1-7.CPM Port D Usage (cont)
- CPM TDM Busses
- Table 1-8.CPM SI1 TDM Busses Wiring
- Table 1-9.CPM SI2 TDM Busses Wiring
- 33Bank of Clocks
- Table 1-10.CPM Bank of Clocks Usage
- Baud Rate Generator
- Table 1-11.CPM Baud Rate Usage
- Ethernet 10/100BaseT
- Table 1-12.Ethernet Signals on the CPM
- 34Table 1-12.Ethernet Signals on the CPM (cont)
- TTY Console Serial Port
- Table 1-13.Asynchronous Console Serial Port Wiring
- User-ProgrammableLEDs
- 35Figure 1-3.Board CPU_LEDs
- Table 1-14. User-ProgrammableLED Control Ports
- 36PowerSpan PCI Configuration Registers
- Table 1-15.PCI Configuration Registers
- 37Table 1-15.PCI Configuration Registers (cont)
- PowerSpan PCI Registers
- Table 1-16.PowerSpan PCI Registers
- 38Table 1-16.PowerSpan PCI Registers (cont)
- PowerSpan Processor Bus Registers
- Table 1-17.PowerSpan Processor Bus Registers
- 39PowerSpan DMA Registers
- Table 1-18.PowerSpan DMA Registers
- 40PowerSpan Miscellaneous Registers
- Table 1-19.PowerSpan Miscellaneous Registers
- 41PowerSpan I²O Registers
- Table 1-20.PowerSpan I²O Registers
- Interrupt Pins and Doorbell Usage
- 42Table 1-21.PowerSpan Interrupt Pin Usage
- PCI to Local Interrupt (ATN)
- 43Local to PCI Interrupt (–INTA)
- Hardware and Software Resets Through the PowerSpan
- Local Space Access From PCI Memory Space
- 45Figure 1-4.Local Space Access From PCI Memory Space
- 46Access to the FLASH EEPROM Through CompactPCI
- PCI Memory Space and I/O Space Access From the PowerQUICC
- 48Figure 1-5.PCI I/O or Memory Space Access from Local Space
- In-situEPLDs Programming
- 49Serial EEPROM Connected to the PowerSpan
- Table 1-22.Serial EEPROM Mapping
- Board Equipment Register
- Table 1-23.Board Equipment Register Layout
- 50Table 1-24.Hardware Configuration Register Field Descriptions
- Field
- 51Vital Product Data (VPD)
- Interphase-SpecificProduction Data and Boot Monitor Parameters
- Table 1-25.FLASH EEPROM Mapping
- 52Table 1-25.FLASH EEPROM Mapping (cont)
- FLASH Addr 1st MAP
- 53Table 1-26.GCM Register Programming (MCLK=12.500 MHz)
- Table 1-27.Transmit Pulse Shape Programming
- 54Table 1-28.QuadFALC Multifunction Port Usage
- 55Table 1-29.Ethernet LEDs
- 56General
- Direct Mode
- Switched Mode
- Pass Through Mode
- 57Figure 1-6.TDM Busses General Structure
- 58Figure 1-7.General Clock Structure (Framer 1 & 2)
- 59Figure 1-8.General Clock Structure (Framer 3 & 4)
- 60Multiplex Direct Mode
- Table 1-30.TDM and Synchronization Signals in Multiplex Direct Mode
- 61Figure 1-9.TDM Busses in Multiplex Direct Mode
- 62Figure 1-10.Clocks in Multiplex Direct Mode (Framer 1 & 2)
- 63Figure 1-11.Clocks in Multiplex Direct Mode (Framer 3 & 4)
- 64Independent Direct Mode
- Table 1-31.TDM and Synchronization Signals in Independent Direct Mode
- 65Table 1-31.TDM and Synchronization Signals in Independent Direct Mode (cont)
- 67Figure 1-12.TDM Busses in Independent Direct Mode
- 68Figure 1-13.Clocks in Independent Direct Mode (Framer 1 & 2)
- 69Figure 1-14.Clocks in Independent Direct Mode (Framer 3 & 4)
- 70Switched Mode
- PA(7) = SWMODE_N
- Table 1-32.TDM and Synchronization Signals in Switched Mode
- 71Figure 1-15.TDM Busses in Switched Mode
- 72Figure 1-16.Clocks in Switched Mode (Framer 1 & 2)
- 73Figure 1-17.Clocks in Switched Mode (Framer 3 & 4)
- 74Pass-ThroughMode
- PA(0) = COMCLK_N
- COMCLK_N = 0)
- TDMd1_TX and TDMa1_TX must be configured as open drain ports
- Table 1-33.TDM and Synchronization Signals in Pass Through Mode
- 75Table 1-33.TDM and Synchronization Signals in Pass Through Mode (cont)
- Unused TDM signals must be tristated
- 76Figure 1-18.TDM Busses in Pass-ThroughMode (1->2& 3->4Example)
- 77Figure 1-19.TDM Busses in Pass-ThroughMode (2->1& 4->3Example)
- 78Figure 1-20.Clocks in Pass-ThroughMode (Framer 1 & 2)
- 79Figure 1-21.Clocks in Pass-ThroughMode (Framer 3 & 4)
8124538 Power-UpInitialization
- 82PowerSpan Register Initialization Through the I²C Serial EEPROM
- Table 2-1.PowerSpan Register Initialization Values in the Serial EEPROM
- 83Table 2-1.PowerSpan Register Initialization Values in the Serial EEPROM (cont)
- Other PowerSpan Initializations
- 84Example 2-1.PowerSpan Interrupt Map Registers Initialization Code
- 85Internal Memory Map Register (IMMR)
- Bus Configuration Register (BCR)
- 86System Protection Control Register (SYPCR)
- 60x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL)
- SIU Module Configuration Register (SIUMCR)
- 87Bus Transfer Error Registers (TESCR1 and L_TESCR1)
- SDRAM Controller and SDRAM Device Initialization
- 88GPCM Controller Initialization
- UPM Controller Programming
- MMU Initialization
- Cache Initialization
- 89I/O Port Initialization
- CPM RCCR Reset
913Programming the Peripherals
- TDM Busses in Multiplexed Direct Mode and in Switched Mode
- 92TDM Busses in Independent Direct Mode
- 93TDM Busses in Pass-ThroughMode
- 95Introduction
- BRGCLK
- BRG7 – TTY Baud-RateGenerator
- 97Introduction
- Master Clock Initialization
- Table 3-1.GCM Register Programming
- TDM Busses General Structure
- 98Multiplexed Direct Mode
- 99Table 3-2.Channel Phase Programming in Multiplexed System Data Streams
- RCLK1 Configuration as TDM Bus Clock
- Table 3-3.QuadFALC RCLK Reference Source for DCO-R
- 100Independent Direct Mode
- 101Switched Mode
- 102Pass-ThroughMode
- 104Common Initialization
- T1 Specific Initialization
- E1/E1-CRC4Common Initialization
- 105E1 Non-CRC4Specific Initialization
- E1-CRC4Specific Initialization
- Clock Synchronization Initialization
- 106Table 3-10.Master Mode Initialization (cont)
- Value Comment
- Transmit Pulse Shape
- Line LED Control
1094Accessing the 4538 on the PCI Side
- 110Example 4-1.Reset and Run Command Routines
- Example 4-2.PCI to Local Interrupt Routines (From the PCI Side)
- 111Example 4-3.Routines Related to Local-to-PCIInterrupt
- 112Example 4-4.Set and Reset FLASH Mode Routine (From PCI Side)
- 113Example 4-5.FLASH Read and Write Routines (From PCI Side)
- 114FLASH EEPROM Programming Algorithms
- Example 4-6.I²C Serial EEPROM Read and Write Routines (From PCI Side)
- 115Avoid the reads. Prefer the writes
- Prefer the bursts
- Prefer DMA transfers
- 116Example:
1175Connectors and Front Panel
- 118Figure 5-3.Connectors and Leds on front panel
- LED Descriptions
- RJ48 Connectors J1 and J2
- 119Table 5-1.RJ48 Connectors J1 and J2
- Signal
- Ethernet 10/100 RJ45 Connector J3
- Table 5-2.Ethernet 10/100 RJ45 Connector
- 120TTY Serial Port J4
- Table 5-3.J4 TTY Serial Connector
- Figure 5-4.TTY connector : 2.5mm stereo jack plug
- PMC Connectors P1 and P2
- Table 5-4.PMC Connector P1
- 121Table 5-4.PMC Connector P1 (cont)
- 122Table 5-5.PMC Connector P2
- 123Table 5-5.PMC Connector P2 (cont)
- 125PMC Connector P4
- Table 5-6.PMC Connector P4
- 126Table 5-6.PMC Connector P4 (cont)
- 128Table 5-7.J5 Debug Port
- 129Figure 5-5.4538 Connectors
- CompactPCI Carrier Card
- Table 5-8.CompactPCI J3 Pin-Out
- 130Table 5-8.CompactPCI J3 Pin-Out(cont)
- Table 5-9.CompactPCI J5 Pin-Out
- 30&,2 30&,2
- 131Custom Carrier Card
- 133Table 5-10.T1/E1/J1 RJ48 Connector
135AMechanical Information A
137Bibliography
143Glossary
- 144Basic Rate Interface
- Board Support Package
- Broadcast and Unknown Server
- Content Addressable Memory
- Constant Bit Rate
- Common Channel Signaling
- COM u Communication or Communications
- Common Part Convergence Sublayer
- CPM u Communication Processing Module
- Cyclic Redundancy Check
- Convergence Sublayer
- Channel Service Unit
- Data Channel
- Data-Link
- Connection Identifier
- Direct Memory Access
- DPRAM u Dual Port Random Access Memory
- Digital Signal level
- 145Data Terminal Equipment
- Emulated LAN
- END u Enhanced Network Driver
- EPLD u Electrically Programmable Logic Device
- End System
- Extended Superframe Format
- Fast serial Communication Controllers
- Fiber Distributed Data Interface
- File Transfer Protocol
- High-Level
- Data Link Control
- Inverse Multiplexing over ATM
- IMMR u Internal Memory Map Register
- Internet Protocol
- Integrated Services Digital Network
- International Organization for Standardization
- 146Local-Area
- Network
- LAN Emulation
- Link Access Procedure, Balanced
- LAN Emulation Client
- LAN Emulation Configuration Server
- LAN Emulation Server
- Local Management Interface
- MCC u Multichannel Communication Controller
- Multiplexer
- Network Termination
- Nonvolatile RAM
- Optical Carrier
- Open System Interconnection
- Peripheral Component Interconnect
- Public Data Network
- 147Protocol Data Unit
- Packet Level Protocol
- PCI Mezzanine Card
- Power-On-Self-Test
- Primary Rate Interface
- Programmable
- Permanent Virtual Circuit or Connection
- Quality of Service
- Random-Access
- Reduced Instruction Set Computing
- Rear Transition Module
- Receive or Receiver
- Segmentation And Reassembly
- SCC u Serial Communication Controller
- Synchronous Digital Hierarchy
- Synchronous Data Link Control
- Service Data Unit
- SDRAM u Synchronous Digital Random Access Memory
- Simple And Efficient AAL
- SIU u Serial Interface Unit
- SMC u Serial Management Controller
- Switched Multimegabit Data Service
- Systems Network Architecture
- Synchronous Optical Network
- Signaling System
- Service Specific Convergence Sublayer
- Synchronous Transport Module level
- 148STS u Synchronous Transport Signal
- Synchronous Transport Signal level
- Switched Virtual Circuit
- Transmission Control Protocol
- Trivial File Transfer Protocol
- Teletypewriter
- Tx u Transmit or Transmitter
- Variable Bit Rate
- Virtual Channel Connection
- Virtual Channel Link
- Virtual Path Identifier
- Wide-Area
149Index