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Interphase Tech 4538 Introduction, BRGCLK, BRG7 – TTY Baud-RateGenerator, MCC Initialization, Clocks and Baud-RateGenerators

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Chapter 3: Programming the Peripherals

Clocks and Baud-Rate Generators

Introduction

The CPM contains eight independent, identical, Baud-Rate Generators (BRGs) that can be used with the FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. In addition, the output of a BRG can be routed to a pin to be used externally.

BRGCLK

The BRGCLK is an internal signal generated in the MPC8260 clock synthesizer specifically for the BRGs, the SPI, and the I2C internal BRG. BRGCLK is itself sourced from VCO_OUT (twice the CPM clock) which is at 266.144 MHz. The DFBRG field of SCCR must be programmed to 01, so that BRGCLK equals VCO_OUT/16 ( = 16.384 MHz). For more information on SCCR and DFBRG fields, see the MPC8260 PowerQUICC II Users Manual.

See Boot Firmware sources: app\asm\startup.asm.

BRG7 – TTY Baud-Rate Generator

The TTY interface is controlled by SMC1.

SMC1 baud-rate generator is BRG7.

Configure the CMXSMR register as follows:

•SMC1 = 0: SMC1 is not connected to TSA.

•Reserved = 0: This bit should be cleared.

•SMC1CS = 01: SMC1 transmit and receive clocks are BRG7.

•SMC2 = 0: SMC2 is not connected to TSA (don’t care).

•Reserved = 0: This bit should be cleared.

•SMC2CS = 00: SMC2 transmit and receive clocks are BRG2 (don’t care).

Final Result of CMXSMR register is 0x10. For more information on CMXSMR fields, see the MPC8260 PowerQUICC II Users Manual.

The DIV16 field of BRGC7 register must be set to 0, so the first BRG7 divider will divided the received BRGCLK clock by 1 and will use the 16.384 MHz clock.

To provide the proper baud-rate value (2400, 4800, 9600,... baud), the SMC1 clock source must be 16 times the rate of the line (see BRGC7 register).

See Boot Firmware sources: app\c\montty.c - Function gwMonTTYOpen.

MCC Initialization

In Multiplexed Direct Mode and in Switched Mode, only MCCs TDMa1 is connected to the framers. TDMa2, TDMbx, TDMcx, and TDMdx are not used. TDMa1 can transport up to 128 MCC channels. This must be configured in the MCCF1 register.

4538 Hardware Reference Manual

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Contents

Page Page Copyright Notice Disclaimer Trademark Acknowledgments Assistance Product Purchased from Reseller Product Purchased Directly from Interphase Corporation END-USERLICENSE AGREEMENT FOR INTERPHASE CORPORATION SOFTWARE IMPORTANT NOTICE TO USER–READCAREFULLY Grant of License: Restrictions on Use: Limitation of Liability: Confidentiality: Termination: Export: U.S. Government Restricted Rights: Contents CHAPTER 2 4538 Power-UpInitialization CHAPTER 3 Programming the Peripherals CHAPTER 4 Accessing the 4538 on the PCI Side CHAPTER 5 Connectors and Front Panel APPENDIX A Mechanical Information List of Figures Page List of Tables Page List of Examples Page Using This Guide NOTE CAUTION WARNING Return WWWMethod FTP Method <directory Page 1Hardware Description 4538 Hardware Structure Figure 1-1.4538 Structure PowerQUICC II Resets System Clocks PCI Local Space Mapping Table 1-1.PCI Local Space Mapping Figure 1-2.Local Space Mapping Interrupts Table 1-2.Local Interrupts Table 1-3.PowerQUICC II Memory Controller Machine Usage Communication Processor Module (CPM) I/O Ports 7DEOHCPM Port A Usage 'LU 7DEOHCPM Port B Usage 7DEOHCPM Port C Usage Table 1-7.CPM Port D Usage Table 1-7.CPM Port D Usage (cont) CPM TDM Busses Table 1-8.CPM SI1 TDM Busses Wiring Table 1-9.CPM SI2 TDM Busses Wiring Bank of Clocks Table 1-10.CPM Bank of Clocks Usage Baud Rate Generator Table 1-11.CPM Baud Rate Usage Ethernet 10/100BaseT Table 1-12.Ethernet Signals on the CPM (cont) TTY Console Serial Port Table 1-13.Asynchronous Console Serial Port Wiring User-ProgrammableLEDs Figure 1-3.Board CPU_LEDs Table 1-14. User-ProgrammableLED Control Ports PowerSpan PCI Configuration Registers Table 1-15.PCI Configuration Registers Table 1-15.PCI Configuration Registers (cont) PowerSpan PCI Registers Table 1-16.PowerSpan PCI Registers Table 1-16.PowerSpan PCI Registers (cont) PowerSpan Processor Bus Registers Table 1-17.PowerSpan Processor Bus Registers PowerSpan DMA Registers Table 1-18.PowerSpan DMA Registers PowerSpan Miscellaneous Registers Table 1-19.PowerSpan Miscellaneous Registers PowerSpan I²O Registers Table 1-20.PowerSpan I²O Registers Interrupt Pins and Doorbell Usage Table 1-21.PowerSpan Interrupt Pin Usage PCI to Local Interrupt (ATN) Local to PCI Interrupt (–INTA) Hardware and Software Resets Through the PowerSpan Local Space Access From PCI Memory Space Page Figure 1-4.Local Space Access From PCI Memory Space Access to the FLASH EEPROM Through CompactPCI PCI Memory Space and I/O Space Access From the PowerQUICC Page Figure 1-5.PCI I/O or Memory Space Access from Local Space In-situEPLDs Programming Serial EEPROM Connected to the PowerSpan Table 1-22.Serial EEPROM Mapping Board Equipment Register Table 1-23.Board Equipment Register Layout Table 1-24.Hardware Configuration Register Field Descriptions Field Vital Product Data (VPD) Interphase-SpecificProduction Data and Boot Monitor Parameters Table 1-25.FLASH EEPROM Mapping Table 1-25.FLASH EEPROM Mapping (cont) FLASH Addr 1st MAP Table 1-26.GCM Register Programming (MCLK=12.500 MHz) Table 1-27.Transmit Pulse Shape Programming Table 1-28.QuadFALC Multifunction Port Usage Table 1-29.Ethernet LEDs General Direct Mode Switched Mode Pass Through Mode Figure 1-6.TDM Busses General Structure Figure 1-7.General Clock Structure (Framer 1 & 2) Figure 1-8.General Clock Structure (Framer 3 & 4) Multiplex Direct Mode Table 1-30.TDM and Synchronization Signals in Multiplex Direct Mode Figure 1-9.TDM Busses in Multiplex Direct Mode Figure 1-10.Clocks in Multiplex Direct Mode (Framer 1 & 2) Figure 1-11.Clocks in Multiplex Direct Mode (Framer 3 & 4) Independent Direct Mode Table 1-31.TDM and Synchronization Signals in Independent Direct Mode Table 1-31.TDM and Synchronization Signals in Independent Direct Mode (cont) Page Figure 1-12.TDM Busses in Independent Direct Mode Figure 1-13.Clocks in Independent Direct Mode (Framer 1 & 2) Figure 1-14.Clocks in Independent Direct Mode (Framer 3 & 4) Switched Mode PA(7) = SWMODE_N Table 1-32.TDM and Synchronization Signals in Switched Mode Figure 1-15.TDM Busses in Switched Mode Figure 1-16.Clocks in Switched Mode (Framer 1 & 2) Figure 1-17.Clocks in Switched Mode (Framer 3 & 4) Pass-ThroughMode PA(0) = COMCLK_N COMCLK_N = 0) TDMd1_TX and TDMa1_TX must be configured as open drain ports Table 1-33.TDM and Synchronization Signals in Pass Through Mode Table 1-33.TDM and Synchronization Signals in Pass Through Mode (cont) Unused TDM signals must be tristated Figure 1-18.TDM Busses in Pass-ThroughMode (1->2& 3->4Example) Figure 1-19.TDM Busses in Pass-ThroughMode (2->1& 4->3Example) Figure 1-20.Clocks in Pass-ThroughMode (Framer 1 & 2) Figure 1-21.Clocks in Pass-ThroughMode (Framer 3 & 4) Page 24538 Power-UpInitialization PowerSpan Register Initialization Through the I²C Serial EEPROM Table 2-1.PowerSpan Register Initialization Values in the Serial EEPROM Table 2-1.PowerSpan Register Initialization Values in the Serial EEPROM (cont) Other PowerSpan Initializations Example 2-1.PowerSpan Interrupt Map Registers Initialization Code Internal Memory Map Register (IMMR) Bus Configuration Register (BCR) System Protection Control Register (SYPCR) 60x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL) SIU Module Configuration Register (SIUMCR) Bus Transfer Error Registers (TESCR1 and L_TESCR1) SDRAM Controller and SDRAM Device Initialization GPCM Controller Initialization UPM Controller Programming MMU Initialization Cache Initialization I/O Port Initialization CPM RCCR Reset Page 3Programming the Peripherals TDM Busses in Multiplexed Direct Mode and in Switched Mode TDM Busses in Independent Direct Mode TDM Busses in Pass-ThroughMode Page Introduction BRGCLK BRG7 – TTY Baud-RateGenerator Page Introduction Master Clock Initialization Table 3-1.GCM Register Programming TDM Busses General Structure Multiplexed Direct Mode Table 3-2.Channel Phase Programming in Multiplexed System Data Streams RCLK1 Configuration as TDM Bus Clock Table 3-3.QuadFALC RCLK Reference Source for DCO-R Independent Direct Mode Switched Mode Pass-ThroughMode Page Common Initialization T1 Specific Initialization E1/E1-CRC4Common Initialization E1 Non-CRC4Specific Initialization E1-CRC4Specific Initialization Clock Synchronization Initialization Table 3-10.Master Mode Initialization (cont) Value Comment Transmit Pulse Shape Line LED Control Page Page 4Accessing the 4538 on the PCI Side Example 4-1.Reset and Run Command Routines Example 4-2.PCI to Local Interrupt Routines (From the PCI Side) Example 4-3.Routines Related to Local-to-PCIInterrupt Example 4-4.Set and Reset FLASH Mode Routine (From PCI Side) Example 4-5.FLASH Read and Write Routines (From PCI Side) FLASH EEPROM Programming Algorithms Example 4-6.I²C Serial EEPROM Read and Write Routines (From PCI Side) Avoid the reads. Prefer the writes Prefer the bursts Prefer DMA transfers Example: 5Connectors and Front Panel Figure 5-3.Connectors and Leds on front panel LED Descriptions RJ48 Connectors J1 and J2 Table 5-1.RJ48 Connectors J1 and J2 Signal Ethernet 10/100 RJ45 Connector J3 Table 5-2.Ethernet 10/100 RJ45 Connector TTY Serial Port J4 Table 5-3.J4 TTY Serial Connector Figure 5-4.TTY connector : 2.5mm stereo jack plug PMC Connectors P1 and P2 Table 5-4.PMC Connector P1 Table 5-4.PMC Connector P1 (cont) Table 5-5.PMC Connector P2 Table 5-5.PMC Connector P2 (cont) Page PMC Connector P4 Table 5-6.PMC Connector P4 Table 5-6.PMC Connector P4 (cont) Page Table 5-7.J5 Debug Port Figure 5-5.4538 Connectors CompactPCI Carrier Card Table 5-8.CompactPCI J3 Pin-Out Table 5-8.CompactPCI J3 Pin-Out(cont) Table 5-9.CompactPCI J5 Pin-Out 30&,2 30&,2 Custom Carrier Card Page Table 5-10.T1/E1/J1 RJ48 Connector Page AMechanical Information A Page Bibliography Page Page Page Page Page Glossary Basic Rate Interface Board Support Package Broadcast and Unknown Server Content Addressable Memory Constant Bit Rate Data Terminal Equipment Emulated LAN END u Enhanced Network Driver EPLD u Electrically Programmable Logic Device End System Local-Area Network LAN Emulation Link Access Procedure, Balanced LAN Emulation Client Protocol Data Unit Packet Level Protocol PCI Mezzanine Card Power-On-Self-Test Primary Rate Interface STS u Synchronous Transport Signal Synchronous Transport Signal level Switched Virtual Circuit Transmission Control Protocol Trivial File Transfer Protocol Index