Chapter 2: 4538 Power-Up Initialization

•APPC = 00: Address Parity pins used as local bus

•CS10PC = 01: –CS10/–BCTL1 used as –BCTL1

•BCTLC = 01: –BCTL0 used as R/–W and –BCTL1 used as –OE

•MMR = 11: External bus requests initially masked at boot, then

MMR = 00: No bus request masking once booted

•LPBSE = 0: LBPS/LGPL4 functions as LGPL4

The resulting register value is SIUMCR=0x4205C000.

Bus Transfer Error Registers (TESCR1 and L_TESCR1)

Since there is no parity checking on the 4538, data errors must be disabled (field DMD=1 in registers TESCR1 and L_TESCR1).

Memory Controllers

The PowerQUICC II includes sophisticated memory controller units: a General Purpose Chip-select Machine (GPCM), three User Programmable Machines (UPMs) and two SDRAM control machines. These units are used on the 4538 to control all the external devices, except the PowerSpan, which is directly a 60x bus compatible device.

The memory controller unit to be used is defined bank per bank. Each bank is defined by its Base Register (BRx) and its Option Register (ORx). The memory machine selection is done in the Option register.

Table 2-2. PowerQUICC II Memory Controller Machine Usage

Element Accessed

Bank

Memory Controller

ORx Value

BRx Value

 

 

 

 

 

)/$6+￿((3520

￿

￿￿[￿EXV￿*3&0

￿[))￿￿￿￿￿￿

￿[))￿￿￿￿￿￿

 

 

 

 

 

￿￿[￿EXV￿0DLQ￿PHPRU\

￿

￿￿[￿EXV￿6'5$0￿PDFKLQH

￿[)&￿￿￿&'￿

￿[￿￿￿￿￿￿￿￿

 

 

 

 

 

4XDG)DOF

￿

￿￿[￿EXV￿830$

￿[))))￿￿￿￿

￿[)￿￿￿￿￿￿￿

 

 

 

 

 

SDRAM Controller and SDRAM Device Initialization

For the SDRAM controller, a specific PowerQUICC II register (PSDMR for the 60x SDRAM controller and LSDMR for the local SDRAM controller) is used to configure operations pertaining to the SDRAM. This register includes several configuration fields and one Operation field (OP). This Operation field must be used to generate all the special accesses needed to initialize the SDRAM, such as the precharges, the refreshes, and the SDRAM internal Mode register write. This will be useful for generating the complete SDRAM initialization sequence.

To generate a special access, one must first set the OP field in the xSDMR register, and then generate a dummy access to the SDRAM memory.

The sequence for SDRAM device initialization is as follows:

•Precharge all banks (OP=101)

4538 Hardware Reference Manual

65