3.3 Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
| DRAM Timing Selectable | By SPD |
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X - CAS Latency Time | (tCL) | Auto |
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X - RAS# to CAS# Delay | (tRCD) | Auto |
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X | - RAS# Precharge | (tRP) | Auto |
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X | - Precharge Delay | (tRAS) | Auto |
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X - System Memory Frequency | Auto |
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► PCI Express Root Port Func | Press Enter |
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| Init Display First |
| PCI Slot |
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| HDMI Port Display |
| DVI |
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| ** VGA Setting ** |
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| Frame Buffer Size |
| 8MB |
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| DVMT Mode |
| DVMT |
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| DVMT/FIXED Memory Size | 128MB |
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:Move Enter:Select | ESC:Exit F1:General Help | ||||
| F5: Previous Values F6: | F7: Optimized Defaults | |||
DRAM Timing Selectable
This item sets the optimal timings for the following four items, depending on the memory module you are using. The default setting “By SPD” configures these four items by reading the contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module stores critical parameter information about the module, such as memory type, size, speed, voltage interface, and module banks.
-CAS Latency Time (tCL)
This item controls the latency between the DRAM read command and the time that the data becomes actually available.
-RAS# to CAS# Delay (tRCD)
This item controls the latency between the DRAM active command and the read/write command.
-RAS# Precharge (tRP)
This item controls the idle clocks after issuing a precharge command to the DRAM.
-Precharge Delay (tRAS)
This item controls the number of DRAM clocks used for the DRAM parameters.
-System Memory Frequency
This item selects the DRAM speed.
BIOS Setup
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