Post Codes
These tables describe the POST codes and descriptions during the POST.
Post Code Range
Phase | POST Code Range |
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SEC | 0x01 - 0x0F |
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PEI | 0x70 - 0x9F |
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DXE | 0x40 - 0x6F |
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BDS | 0x10 - 0x3F |
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SMM | 0xA0 - 0xBF |
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S3 | 0xC0 - 0xCF |
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ASL | 0x51 - 0x55 |
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| 0xE1 - 0xE4 |
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PostBDS | 0xF9 - 0xFE |
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InsydeH2ODDT™ | 0xD0 - 0xD7 |
Reserve |
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OEM Reserve | 0xE8 - 0xEB |
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Reserved | 0xD8 - 0xE0 |
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| 0xE5 - 0xE7 |
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| 0xEC - 0xF8 |
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SEC Phase POST Code Table
Functionality Name (Include\ | Phase | Post | Description | |
PostCode.h) | Code | |||
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| |||
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| |
SEC_SYSTEM_POWER_ON | SEC | 1 | CPU power on and switch to | |
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| Protected mode | |
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| |
SEC_BEFORE_MICROCODE_PATCH | SEC | 2 | Patching CPU microcode | |
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SEC_AFTER_MICROCODE_PATCH | SEC | 3 | Setup Cache as RAM | |
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SEC_ACCESS_CSR | SEC | 4 | PCIE MMIO Base Address initial | |
SEC_GENERIC_MSRINIT | SEC | 5 | CPU Generic MSR initialization | |
SEC_CPU_SPEEDCFG | SEC | 6 | Setup CPU speed | |
SEC_SETUP_CAR_OK | SEC | 7 | Cache as RAM test | |
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| |
SEC_FORCE_MAX_RATIO | SEC | 8 | Tune CPU frequency ratio to | |
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| maximum level | |
SEC_GO_TO_SECSTARTUP | SEC | 9 | Setup BIOS ROM cache | |
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| |
SEC_GO_TO_PEICORE | SEC | 0A | Enter Boot Firmware Volume | |
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NOTE: The color bar items indicate 3rd party related functions that are platform dependent.
Chapter 4 | 147 |
