Acer 6492 manual LCD Power On Sequence, Bios ROM WX25X80VSSIG, Audio Codec

Core System

Item	Description	Specifications
6	System	Package: DDR2 SDRAM in 84-ball FBGA
	memory	Supply voltage: 1.8V±0.1V
		Speed: 667MHz / 533MHz (CL=4 or 5)
		Refresh:
		• Auto & self refresh capability
		• 7.8µs(max),Average periodic refresh interval
		Features:
		• Data is read or written on both clock edges
		• Address and control signals are fully synchronous to positive clock edge
7	BIOS ROM	WX25X80VSSIG
		ROM type: Organized as 8M×1
		Package: 8 PIN SOIC (8.1mm×5.38mm)
		Block-Erase: uniform 64 KByte blocks
		Supply current:
		• Active current =5 mA (Typical)
		• Standby current=1 uA (Typical)
		Superior reliability:
		• Endurance: 100,000 cycles (Typical)
		• Greater than 20 years data retention

DISPLAY SUBSYSTEM

The 965GM contains a dual-channel 24-bit LVDS interface. Notice that for designs implementing only a single LVDS channel, the LOWER channel of the interface should be used.

•Integrated dual 24-bit LVDS interface.

•595 Mbps/channel with 85 MHz pixel clock rate.

•FPDI-2 compliant; compatible with receivers from National Semiconductor, Texas Instruments, and THine.

•OpenLDI compliant excluding DC balancing.

•Programmable internal spread spectrum controller for the LVDS signals.

•LVDS eye pattern to improve testability of LVDS module

LCD Power On Sequence

LCD timing must follow up below specification to meet the minimum requirements.

•ENAVDD(LCDVCC)´ SHFCLK(DATA)--´BLON (power on sequence)

•BLON´SHFCLK(DATA)--´ENAVDD(LCDVCC) (power off sequence)

Note A: This timing depends on LCD specification

AUDIO SUBSYSTEM

Audio Codec

Audio chip: Realtek ALC268

Package: 48-pin LQFP 'Green' package

Features:

•All ADCs support 44.1K/48K/96K/192kHz sample rate

•All ADCs support 44.1K/48K/96kHz sample rate

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