POST | Function | Phase | Component | |
Code | ||||
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0x6B | If CMOS is bad, load Custom Defaults from flash into CMOS. If | LBT | Core | |
| successful, reboot. |
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0x3C | If CMOS is valid, load chipset registers with values from | LBT | Core | |
| CMOS, otherwise load defaults and display Setup prompt. If |
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| Auto Configuration is enabled, always load the chipset |
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| registers with the Setup defaults (Rel 6.0). |
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0x3D | Load alternate registers with CMOS values | LBT | Core | |
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0x42 | Initialize interrupt vectors 0 thru 77h | LBT | Core | |
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0x46 | Verify the ROM copyright notice | LBT | Core | |
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0x45 | Initialize all motherboard devices. | LBT | Core | |
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0x49 | 1. Size the PCI bus topology and set bridge bus numbers. | LBT | Core |
2.Set the system max bus number.
3.Write a 0 to the command register of every PCI device.
4.Write a 0 to all 6 base registers in every PCI device.
5.Write a
0xC6 | Initialize note dock | LBT | Core |
0xC5 | PnPnd dual CMOS (optional) | LBT | Core |
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0x48 | Verify that the equipment specified in the CMOS matches the | LBT | Core |
| hardware currently installed. If the monitor type is set to 00 |
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| then a video ROM must exist. If the monitor type is 1 or 2 set |
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| the video switch to CGA. If monitor type 3, set the video switch |
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| to m |
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0xD1 | Initialize BIOS stack | LBT | Core |
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0xD3 | Setup E820h and WAD memory map | LBT | Core |
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0x24 | Set | LBT | Core |
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0xCC | Redirect Int 10h to enable target board to use a remote serial | LBT | Core |
| video (PICO BIOS). |
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0x8A | Initialize Extended BIOS Data Area and initialize the mouse. | LBT | Core |
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0x9D | Initialize Security Engine. | LBT | Core |
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0x55 | USB Initialization | LBT | Core |
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0x52 | Verify keyboard reset. | LBT | Core |
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0x54 | Initialize keystroke clicker if enabled in Setup. | LBT | Core |
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0x76 | Check status bits for | LBT | Core |
| messages on the screen. |
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0x4A | Initialize all video adapters in system | LBT | Core |
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0x4C | Shadow video BIOS ROM if specified by Setup, and CMOS is | LBT | Core |
| valid and the previous boot was OK. |
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0x59 | Register POST Display Services, fonts, and languages with | LBT | Core |
| the POST Dispatch Manager. |
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0x57 | Initialize 1394 Firewire | LBT | Core |
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0xD6 | Initialize PC card | LBT | Core |
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0x58 | Test for unexpected interrupts. First do an STI for hot | LBT | Core |
| interrupts. Secondly, test the NMI for an unexpected interrupt. |
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| Thirdly, enable the parity checkers and read from memory, |
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| checking for an unexpected interrupt. |
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0x3F | ROMPolit memory init | LBT | Core |
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0xC4 | Install the IRQ vectors (Sever Hotkey) | LBT | Core |
140 | Chapter 4 |
