Acer 6530 manual Lbt

POST	Function	Phase	Component
Code
0x22	TCG Physical Presence execution	DXE	TCG
0xB1	TCG DXE common pass through	DXE	TCG
0xE3	First Legacy BIOS Task table for legacy reset	LBT	Core
0x20	Verify that DRAM refresh is operating by polling the refresh bit	LBT	Core
	in PORTB.
0xDA	Dummy PCIE Init entry, now handled by driver	LBT	Core
0x29	PMM (POST Memory Manager) init	LBT	Core
0xE5	WHEA init	LBT	Core
0x33	PDM (Post Dispatcher Manager) init	LBT	Core
0x01	IPMI init	LBT	Core
0xD8	ASF Init	LBT	Core
0x09	Set in-POST flag in CMOS that indicates we are in POST. If	LBT	Core
	this bit is not cleared by postClearBootFlagJ(AEh), the
	TrustedCore on next boot determines that the current
	configuration caused POST to fail and uses default values for
	configuration.
0x2B	Enhanced CMOS init	LBT	Core
0xE0	EFI Variable Init	LBT	Core
0xC1	PEM (Post Error Manager) init	LBT	Core
0x3B	Debug Service Init (ROM Polit)	LBT	Core
0xDC	POST Update Error	LBT	Core
0x3A	Autosize external cache and program cache size for enabling	LBT	Core
	later in POST.
0x0B	Enable CPU cache. Set bits in cmos related to cache.	LBT	Core
0x0F	Enable the local bus IDE as primary or secondary depending	LBT	Core
	on other drives detected.
0x10	Initialize Power Management.	LBT	Core
0x14	Verify that the 8742 keyboard controller is responding. Send a	LBT	Core
	self-test command to the 8742 and wait for results. Also read
	the switch inputs from the 8742 and write the keyboard
	controller command byte.
0x1A	Initialize DMA command register with these settings:	LBT	Core

1.Memory to memory disabled

2.Channel 0 hold address disabled

3.Controller enabled

4.Normal timing

5.Fixed priority

6.Late write selection

7.DREQ sense active

8.DACK sense active low. Initialize

0x22	Reset the keyboard.	LBT	Core
0x40	Test A20 line	LBT	Core
0x67	Quick initialization of all Application Processors in a multi-	LBT	Core
	processor system
0x32	Compute CPU speed.	LBT	Core
0x69	Initialize the handler for SMM.	LBT	Core

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