ADC ADDC1 instruction manual

The Auto mode allows the ADC1 to lock to an external clock reference. In Auto mode, the ADC1 will follow changes in sample rate, and/or changes in the type of reference signal (AES, SPDIF, word clock, or super clock).

When a clock reference is not available, the Internal mode must be used, and a sample- rate must be selected (44.1, 48, 88.2, 96, 176.4, or 192 kHz). When the Internal mode is active, the ADC1 is acting as clock master, will only operate at the selected sample rate, and will ignore any signal at the clock reference input. If Internal mode is used, all devices connected to the ADC1 digital outputs will need to be configured to lock to the ADC1. Use the clock output on the back of the ADC1 if the connected devices require word clock.

The Benchmark UltraLock system is 100% jitter immune. The A/D conversion clock is totally isolated from the AES/EBU, SPDIF, ADAT, WC, and super clock interfaces. This topology outperforms two-stage PLL designs. In fact, no jitter-induced artifacts can be detected using an Audio Precision System 2 Cascade test set. Measurement limits include detection of artifacts as low as -140 dBFS, application of jitter amplitudes as high as

12.75unit intervals (UI) and application of jitter over a frequency range of 2 Hz to 200 kHz. A poor-quality clock reference will not degrade the jitter performance of the ADC1. In addition, the AES/EBU receiver IC has been selected for its ability to decode signals in the presence of very high levels of jitter. The Benchmark UltraLock system delivers consistent performance under all operating conditions.

The ADC1 is designed to perform gracefully in the presence of errors and interruptions at the clock reference input. The ADC1 follows an audio-always design philosophy. Audio is present at the outputs shortly after applying power to the unit. The ADC1 will even lock to and AES/EBU signal that has its sample-rate status bits set incorrectly. Sample rate is determined by measuring the incoming signal. Lack of sample rate status bits or incorrectly set status bits will not cause loss of audio.

ADC1 Instruction Manual

The ADC1 is phase accurate between channels, and between other ADC1 boxes when locked to AES/EBU or word clock reference signals. The word clock output from one ADC1 may be connected to the clock input on another ADC1 to expand the number of phase-accurate conversion channels.

Page 5