AMD D900K manual LPC Super I/ O NS87393, Sheet 22, Fwhflash#

Schematic Diagrams

LPC SUPER I/ O NS87393

+3VS

C559

C497

C508

SA0

12

U8

13

SD0

0.1UF

0.1UF

0.1UF

A0

O0

SA1

11

14

SD1

SA2

10

A1

O1

15

SD2

U46

14 39 63 88

PD[0..7]

SA3

9

A2

O2

17

SD3

LPC_AD[0..3]

PD[0..7]

(23)

SA4

8

A3

O3

18

SD4

(13,24) LPC_AD[0..3]

VDD VDD VDD VDD

SA5

7

A4

O4

19

SD5

A5

O5

LPC_AD0

15

52

PD0

SA6

6

A6

O6

20

SD6

LAD0

PD0/INDEX#

SA7

5

21

SD7

LPC_AD1

16

50

PD1

SA8

27

A7

O7

LPC_AD2

17

LAD1

PD1/TRK0#

48

PD2

+3VS

SA9

26

A8

LPC_AD3

18

LAD2

PD2/WP#

46

PD3

SA10

23

A9

PCLKSIO

LAD3

PD3/RDATA#

45

PD4

SA11

25

A10

(2)

PCLKSIO

8

PD4/DSKCHG#

44

PD5

SA12

4

A11

PCIRST#

9

LCLK

PD5/MSEN0

43

PD6

SA13

28

A12

(11,17,19,24,27,29)

PCIRST#

LPC_FRAME#

12

LRESET#

PD6/DRATE0

42

PD7

R540

U52

+5VS

SA14

29

A13

32

+5VS

(13,24)

LPC_FRAME#

LPC_DRQ#

11

LFRAME#

PC87393

PD7/MSEN1

36

PSLCT

+3VS

10K

SA16

2

A15

(13)

+3VS

BID0

47K

6

LPCPD#

PNF/XRDY

4.7K

SA15

3

A14

LPC_DRQ#

R419

7

LDRQ#

35

R389

FLASH#

5

R544

1K

BIOSCS#

A16

VCC

SA17

(12,17,24)

SERIRQ

SERIRQ

10

CLKRUN#/GPIO36

SLCT/WGATE#

37

PPE

PSLCT

(23)

1

VCC

22

30

FLASH#

19

SERIRQ

PE/WDATA#

40

PBUSY

PPE

(23)

IN1

4

MEMR#

24

CE

A17

SMI#/GPIO35

BUSY_WAIT#/MTR1#

41

PACK#

PBUSY

(23)

MEMW#

2

OUT

SA18

1

OE

16

C770

(2)

SIOCLK48

SIOCLK48

R395

0

20

CLKIN

ACK#/DR1#

47

PSLIN#

PACK#

(23)

3

IN2

WBIOS#

31

VPP

SIO48M

R401

33(R)

SLIN#_ASTRB#/STEP#

49

PINIT#

PSLIN#

(23)

GND

PGM

GND

0.1UF

DISKCHG#

INIT#/DIR#

51

PPERR#

PINIT#

(23)

TC7S32F

C755

MX29F004

21

DSKCHG#

ERR#/HDSEL#

53

PATFD#

PPERR#

(23)

HDSEL#

22

AFD#_DSTRB#/DENSEL

54

PSTB#

PATFD#

(23)

0.1UF

T

RDATA#

23

HDSEL#

STB#_WRITE#

PSTB#

(23)

WRPRT#

24

RDATA#

DCDA#

TRK0#

25

WP#

55

DCDA#

(23)

+3VS

WGATE#

26

TRK0#

DCD1#

56

DSRA#

T

WDATA#

27

WGATE#

DSR1#

57

SINA

DSRA#

(23)

T

STEP#

28

WDATA#

SIN1

58

RTSA#

SINA

(23)

T

DIR#

29

SETP#

RTS1#/TEST

59

SOUTA

RTSA#

(23)

T

DRV0#

30

DIR#

SOUT1/XCNF0

60

CTSA#

SOUTA

(23)

C836

C835

C831

C832

T

MTR0#

31

DR0#

CTS1#

61

DTRA

CTSA#

(23)

T

INDEX#

32

MTR0#

DTR1#_BOUT1/BADDR

62

RIA#

DTRA

(23)

0.1U

0.1U

0.1U

0.1U

3MODE#

33

INDEX#

RI1#

RIA#

(23)

34

DENSEL

T

DRATE0/IRSL2

70

IRTX

IRTX

69

IRRX

1

U10

32

SA0

95

XA0/GPIO20

IRRX1

68

IRMODE

SA1

94

IRRX2_IRSL0

67

T 0(R)

(11,17,19,24,27,29)

PCIRST#

PCIRST#

2

VPP

VCC

31

PCLK_FWH

8.2K

PCLK_FWH

(2)

SA2

93

XA1/GPIO21

IRSL1

66

R420

PME#

(12,17,19,20,24,29)

R570

8.2K

3

RST#

CLK

30

R564

SA3

92

XA2/GPIO22

IRSL3/PWUREQ#

+3V

R571

8.2K

4

FGPI3

FGPI4

29

R565

8.2K

SA4

91

XA3/GPIO23

3

SD0

R575

8.2K

5

FGPI2

IC

28

SA5

90

XA4/GPIO24/XSTB0#

5 U12

R576

8.2K

6

FGPI1

GNDA

27

SA6

87

XA5/XSTB1#/XCNF2

XD0/GPIO00/JOYABTN1

2

SD1

7

FGPI0

VCCA

26

SA7

86

XA6/GPIO26/PRIQA/XSTB2#

XD1/GPIO01/JOYBBTN1

1

SD2

2

4

8

WP#

GND

25

R566

10K

SA8

85

XA7/GPIO27/PIRQB

XD2/GPIO02/JOYAY

100

SD3

(13) FWH_FLASH#

9

TBL#

VCC

24

SA9

84

XA8/GPIO30/PIRQC

XD3/GPIO03/JOYBY

99

SD4

3

10

ID3

INIT#

23

LPC_FRAME#

SA10

83

XA9/GPIO31/MTR1#/PIRQD

XD4/GPIO04/JOYBX

98

SD5

11

ID2

FWH4

22

SA11

82

XA10/GPIO32/XIORD#/MDRX

XD5/GPIO05/JOYAX

97

SD6

12

ID1

RFU

21

SA12

81

XA11/GPIO33/XIOWR#/MDTX

XD6/GPIO06/JOYBBTN0

96

SD7

7S14(R)

LPC_AD0

13

ID0

RFU

20

SA13

80

XA12/GPIO10/JOYABTN1/RI2#

XD7/GPIO07/JOYABTN0

MEMW#

LPC_AD1

14

FWH0

RFU

19

SA14

79

XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2

4

LPC_AD2

15

FWH1

RFU

18

SA15

78

XA14/GPIO12/JOYAY/CTS2#

XWR#/XCNF1

5

MEMR#

PCLKSIO

R577

8.2K

16

FWH2

RFU

17

LPC_AD3

SA16

77

XA15/GPIO13/JOYBY/SOUT2

XRD#/GPIO34/WDO#

73

T BID1

+3VS

GND

FWH3

SA17

76

XA16/GPIO14/JOYBX/RTS2#

XIOWR#/XCS1#/MTR1#/DRATE0

71

FWH32(R)

SA18

75

XA17/GPIO15/JOYAX/SIN2

XIORD#/GPIO37/IRSL2/DR1#

72

BIOSCS#

SOCKET PLCC32

74

XA18/GPIO16/JOYBBTN0/DSR2#

XCS0#/DR1#/XDRY/GPIO25

R407

T

XA19/DCD2#/JOYABTN0/GPIO17

C521

0.1U

VSS VSS VSS VSS

10(R)

Y6

PC87393

13 38 64 89

C522

FIRVCC

1

4

10PF(R)

L51

CNT

VCC

VCC3S

2

3

SIO48M

+3VS

FCM2012V121

GND

OUT

C917

C922

48MHZ-OSC(R)

PLACE NEAR PC87393

4 3 2 1

4 3 2 1

4.7U(0805)

10U(0805)(R)

RN73

RN72

+5VS

+3VS

+3VS

+3VS

8P4R-18

8P4R-18

RP13

SA3

3MODE#

FIRGND

1

1

10

10

SA8

R388

10K

R298

R301

5 6 7 8

5 6 7 8

SA4

2

9

R387

10K

INDEX#

MEMW# R439

SA5

3

2

9

8

SA11

R454

10K

BIOSCS#

10K(R)

SD0

4

3

8

7

SA7

R438

10K

MEMR#

4.7K(R)

47K

5

4

7

6

SA6

R437

10K

R417

R421

C935

C932

5

6

SOUTA

10(R)

10K(R)

10

10U(0805)

1000P

10P8R-8.2K

R408

10K

BID0

U38

RP12

RN38

8P4R-10K

XBUS RESET CONFIGURATION

IRRX

SA17

BID1

8

RXD

LEAD

1

1

10

10

8

1

TRK0#

DTRA

IRMODE

FIRGND

SA13

2

9

SA18

7

2

WRPRT#

R409

10K(R)

3

FIR_SEL

MDO

4

R704

2.2K

SA14

3

2

9

8

SA16

6

3

RDATA#

BASE ADDRESS CONFIGURATION

R418

R440

SA9

4

3

8

7

SA15

5

4

DISKCHG#

10K

10K

IRTX

9

TXD

MD1

5

R705

2.2K

5

4

7

6

SA12

DTRA# PULL-UP :4E

5

6

RN39

8P4R-47K

DTRA# PULL-DOWN :2E (DEFAULT)

11

FIRGND

10P8R-8.2K

8

RTSA#

R402

4.7K(R)

R302

NC

GND

AGNDD

VCC

SD2

1

1

10

10

1

CTSA#

6

3

DSRA#

GNDPAD

RP14

7

2

SINA

SD1

2

2

9

9

SD3

5

4

DCDA#

4.7K

6

7

2

HSDL-3602 1

SA1

3

8

SD4

SA2

4

3

8

7

SA10

+3V

JA1

5

4

7

6

SA0

1

2

C916

0.1UF

5

6

+5VS

+3V

(11,17,18,19,20,21,24,29,32,33)

10P8R-8.2K

SHORT-A

C342

0.047U

FIRGND

R451

8.2K

SD5

+5VS

(11,12,14,15,16,21,24,29,31,32,33)

T

C343

10UF/10V

FIRVCC

R452

8.2K

SD6

+3VS

R453

8.2K

SD7

+3VS

(2,8,9,10,11,12,13,14,15,16,19,20,21,24,25,27,29,31,32,33)

Sheet 22 of 40

LPC SUPER I/ O

NS87393

B.Schematic Diagrams

LPC SUPER I/ O NS87393 B - 23