Analog Devices ADE7753 manual z, z

ADE7753
–21–
REV. PrC 01/02
PRELIMINARY TECHNICAL DATA
ENERGY CALCULATIONENERGY CALCULATION
ENERGY CALCULATIONENERGY CALCULATION
ENERGY CALCULATION
As stated earlier, power is defined as the rate of energy flow.
This relationship can be expressed mathematically as
Equation 5.
P=dE
dt
(5)
Where P = Power and E = Energy.
Conversely Energy is given as the integral of Power.
E= Pdt
z
(6)
The ADE7753 achieves the integration of the Active Power
signal by continuously accumulating the Active Power signal
in an internal non-readable 56-bit Energy register. The
Active Energy register (AENERGY[23:0]) represents the
upper 24 bits of this internal register. This discrete time
accumulation or summation is equivalent to integration in
continuous time. Equation 7 below expresses the relationship
E= dt Lim
p(t) T0n0
z∑
=×
R
S
|
T
|
U
V
|
W
|
→=
∞
pnT T
()
(7)
Where n is the discrete time sample number and T is the
sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7753 is 1.1µs (4/CLKIN). As well as
calculating the Energy this integration removes any sinusoi-
dal components which may be in the Active Power signal.
Figure 35 shows a graphical representation of this discrete
time integration or accumulation. The Active Power signal
in the Waveform register is continuously added to the internal
Active Energy register. This addition is a signed addition,
therefore negative energy will be subtracted from the Active
Energy contents.
4
CLKIN
time (nT)
WAVEFORM
REGISTER
VALUES
OUTPUT LPF2
T
LPF2
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
+
+
Σ
Active Power
Signal - P*
Current Channel
Voltage Channel
APOS [15:0]
0
15
2
5
2
6
sgn 2
-8
2
-7
2
-6
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
AENERGY[23:0] REGISTER
52 0
AENERGY[23:0]
WDIV[0:7]
23 0
Figure 35 – ADE7753 Active Energy Calculation
The output of the multiplier is divided by WDIV. If the value
in the WDIV register is equal to 0 then the internal Active
Energy register is divided by 1. WDIV is an 8-bit unsigned
register. After dividing by WDIV, the active energy is
accumulated in a 53-bit internal energy accumulation regis-
ter. The upper 24 bit of this register is accessible through a
read to the Active Energy register (AENERGY[23:0]). A
read to the RAENERGY register will return the content of
the AENERGY register and the upper 24-bit of the internal
register is clear after a read to AENERGY register.
As shown in Figure 35, the Active Power signal is accumu-
lated in an internal 53-bit signed register.
The Active Power signal can be read from the Waveform
register by setting MODE[14:13] = 0,0 and setting the
WSMP bit (bit 3) in the Interrupt Enable register to 1. Like
the Channel 1 and Channel 2 waveform sampling modes the
waveform date is available at sample rates of 27.9kSPS,
14kSPS, 7kSPS or 3.5kSPS—see Figure 22.
Figure 36 shows this energy accumulation for full scale
signals (sinusoidal) on the analog inputs. The three curves
displayed, illustrate the minimum period of time it takes the
energy register to roll-over when the Active Power Gain
register contents are 7FFh, 000h and 800h. The Watt Gain
register is used to carry out power calibration in the ADE7753.
As shown, the fastest integration time will occur when the
Watt Gain register is set to maximum full scale, i.e., 7FFh.
00,0000h
7F,FFFFh
80,0000h
3F,FFFFh
40,0000h
AENERGY[23:0]
Time
(minutes)
WGAIN = 7FFh
WGAIN = 000h
WGAIN = 800h
100 20067 133
Figure 36 - Energy register roll-over time for full-scale
power (Minimum & Maximum Power Gain)
Note that the energy register contents will roll over to full-
scale negative (800000h) and continue increasing in value
when the power or energy flow is positive - see Figure 36.
Conversely if the power is negative the energy register would
under flow to full scale positive (7FFFFFh) and continue
decreasing in value.
By using the Interrupt Enable register, the ADE7753 can be
configured to issue an interrupt (IRQ) when the Active
Energy register is half-full (positive or negative) or when an
over/under flow occurs.
Integration time under steady loadIntegration time under steady load
Integration time under steady loadIntegration time under steady load
Integration time under steady load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
WGAIN register set to 000h, the average word value from
each LPF2 is CCCCDh - see Figure 31. The maximum
positive value which can be stored in the internal 53-bit
register is 2
52
- 1 or F,FFFF,FFFF,FFFFh before it over-
flows, the integration time under these conditions with
WDIV=0 is calculated as follows:
sminss.
CCCCDh
FFFFh,FFFF,FFFF,F
Time
1006000121==
m
´=
When WDIV is set to a value different from 0, the integration
time varies as shown on Equation 8.
Time = Time
WDIV=0
x WDIV (8)