Analog Devices ADE7753 () ()

ADE7753

–25–

REV. PrC 01/02

PRELIMINARY TECHNICAL DATA

Reactive

Power

Active

Power

Apparent

Power

Figure 42 - Power triangle

()()

θω

ω

+=

=

tti

ttv

sinI2)(

sinV2)(

rms

(19)

)2cos()cos()(

)()()(

θωθ

+−=

×=

tIVIVtp

titvtp

rmsrmsrmsrms

(20 )

The Apparent Power (AP) is defined as V

rms

x I

rms

. This

expression is independent from the phase angle between the

current and the voltage.

Figure 43 illustrates graphically the signal processing in each

phase for the calculation of the Apparent Power in the

ADE7753.

0.5V / GAIN2

0.5V / GAIN1

Current RMS Signal - i(t)

Voltage RMS Signal - v(t)

MULTIPLIER

Apparent Power

Signal - P

Irms

Vrms

00h

D1B71h

VAGAIN

1CF68Ch

Figure 43 - Apparent Power Signal Processing

The gain of the Apparent Energy can be adjusted by using the

multiplier and VA Gain register (VAGAIN[11:0]). The gain

is adjusted by writing a 2’s complement, 12-bit word to the

VAGAIN register. Below is the expression that shows how

the gain adjustment is related to the contents of the VA Gain























+×= 12

1VAGAIN

PowerApparentVAGAINOutput

For example when 7FFh is written to the VA Gain register

the Power output is scaled up by 50%. 7FFh = 2047d,

2047/2

= 0.5. Similarly, 800h = -2047 Dec (signed 2’s

Complement) and power output is scaled by –50%.

The Apparent Power is calculated with the Current and

Voltage RMS values obtained in the RMS blocks of the

ADE7753. Shown in Figure 44 is the maximum code

(Hexadecimal) output range of the Apparent Power signal.

Note that the output range changes depending on the contents

of the Apparent Power Gain registers. The minimum output

range is given when the Apparent Power Gain register

content is equal to 800h and the maximum range is given by

writing 7FFh to the Apparent Power Gain register. This can

be used to calibrate the Apparent Power (or Energy) calcu-

lation in the ADE7753 -see Apparent Power calculation.

00000h

D1B71h + 50% FS

+ 75% FS

+ 25% FS

13A929h

68DB9h

VAGAIN[11:0]

000h 7FFh 800h

Apparent Power

Calibration Range

Apparent Power ± 100% FS

Apparent Power ± 150% FS

Apparent Power ± 50% FS

Voltage and Current channel inputs: 0.5V / GAIN

Figure 44- Apparent Power Calculation Output range

Apparent Power Offset CalibrationApparent Power Offset Calibration

Apparent Power Offset Calibration

Each RMS measurement includes an offset compensation

RMS value -see Channel 1 RMS calculation and Channel 2 RMS

calculation. The channel 1 and channel 2 RMS values are then

multiplied together in the Apparent Power signal processing.

As no additional offsets are created in the multiplication of

the RMS values, there is no specific offset compensation in

the Apparent Power signal processing. The offset compensa-

tion of the Apparent Power measurement is done by calibrating

each individual RMS measurements.

APPARENT ENERGY CALCULATIONAPPARENT ENERGY CALCULATION

APPARENT ENERGY CALCULATION

The Apparent Energy is given as the integral of the Apparent

Power.

dttPowerApparentEnergyApparent ∫

=)(

(21)

The ADE7753 achieves the integration of the Apparent

Power signal by continuously accumulating the Apparent

Power signal in an internal 52-bit register. The Apparent

Energy register (VAENERGY[23:0]) represents the upper

24 bits of this internal register. This discrete time accumu-

lation or summation is equivalent to integration in continuous

time. Equation 23 below expresses the relationship











×= ∑

∞

→0

0)(

TTnTPowerApparentLimEnergyApparent

(22)

Where n is the discrete time sample number and T is the

sample period.

The discrete time sample period (T) for the accumulation

Figure 44 shows a graphical representation of this discrete

time integration or accumulation. The Apparent Power

signal is continuously added to the internal register. This

addition is a signed addition even if the Apparent Energy

remains theoretically always positive.