Analog Devices ADE7753

ADE7753

–28–REV. PrC 01/02

PRELIMINARY TECHNICAL DATA

CLKIN FREQUENCYCLKIN FREQUENCY

CLKIN FREQUENCY

In this datasheet, the characteristics of the ADE7753 is shown

with CLKIN frequency equals 3.579545 MHz. However, the

ADE7753 is designed to have the same accuracy at any

CLKIN frequency within the specified range. If the CLKIN

frequency is not 3.579545MHz, various timing and filter

characteristics will need to be redefined with the new CLKIN

frequency. For example, the cut-off frequencies of all digital

filters (LPF1, LPF2, HPF1, etc.) will shift in proportion to

the change in CLKIN frequency according to the following

equation:

MHz

FrequencyCLKIN

FrequencyOriginalFrequencyNew 579545.3

×=

(25)

The change of CLKIN frequency does not affect the timing

characteristics of the serial interface because the data transfer

is synchronized with serial clock signal (SCLK). But one

needs to observe the read/write timing of the serial data

transfer-see ADE7753 Timing Characteristics. Table III lists

various timing changes that are affected by CLKIN fre-

quency.

Table III

Frequency dependencies of the ADE7753 parameters

ParameterParameter

Parameter CLKIN dependencyCLKIN dependency

CLKIN dependencyCLKIN dependency

CLKIN dependency

Nyquist frequency for CH 1&2 ADCs CLKI N/8

PHCAL resolution (seconds per LSB) 4/CLKIN

Active Energy register update rate (Hz) CLKI N/4

Waveform sampling rate (Number of samples per second)

WAVSEL 1,0 = 0 0 CLKIN/128

0 1 CLKIN/256

1 0 CLKIN/512

1 1 CLKIN/1024

Maximum ZXTOUT period 524,288/CLKIN

SUSPENDING THE ADE7753 FUNCTIONALITYSUSPENDING THE ADE7753 FUNCTIONALITY

SUSPENDING THE ADE7753 FUNCTIONALITY

The analog and the digital circuit can be suspended sepa-

rately. The analog portion of the ADE7753 can be suspended

by setting the ASUSPEND bit (bit 4) of the Mode register

to logic high See Mode Register. In suspend mode, all

waveform samples from the ADCs will be set to zeros. The

digital circuitry can be halted by stopping the CLKIN input

and maintaining a logic high or low on CLKIN pin. The

ADE7753 can be reactivated by restoring the CLKIN input

and setting the ASUSPEND bit to logic low.

CHECKSUM REGISTERCHECKSUM REGISTER

CHECKSUM REGISTER

The ADE7753 has a Checksum register (CHECKSUM[5:0])

to ensure the data bits received in the last serial read operation

are not corrupted. The 6-bit Checksum register is reset

before the first bit (MSB of the register to be read) is put on

the DOUT pin. During a serial read operation, when each

data bit becomes available on the rising edge of SCLK, the

bit will be added to the Checksum register. In the end of the

serial read operation, the content of the Checksum register

will equal to the sum of all ones in the register previously

read. Using the Checksum register, the user can determine

if an error has occured during the last read operation.

Note that a read to the Checksum register will also generate

a checksum of the Checksum register itself.

CHECKSUM REGISTER

CONTENT OF REGISTER (n-bytes)

DOUT

ADDR: 3Eh

Figure 48– Checksum register for Serial Interface Read