ADE7753
–30–REV. PrC 01/02
PRELIMINARY TECHNICAL DATA
Figure 52 – Serial Interface Write Timing Diagram
Figure 53—12 bit Serial Write Operation
ADE7753 Serial Read OperationADE7753 Serial Read Operation
ADE7753 Serial Read OperationADE7753 Serial Read Operation
ADE7753 Serial Read Operation
During a data read operation from the ADE7753 data is
shifted out at the DOUT logic output on the rising edge of
SCLK. As was the case with the data write operation, a data
read must be preceded with a write to the Communications
register.
With the ADE7753 in communications mode (i.e. CS logic
low) an eight bit write to the Communications register first
takes place. The MSB of this byte transfer is a 0, indicating
that the next data transfer operation is a read. The LSBs of
this byte contain the address of the register which is to be
read. The ADE7753 starts shifting out of the register data on
the next rising edge of SCLK – see Figure 54. At this point
the DOUT logic output leaves its high impedance state and
starts driving the data bus. All remaining bits of register data
are shifted out on subsequent SCLK rising edges. The serial
interface also enters communications mode again as soon as
the read has been completed. At this point the DOUT logic
output enters a high impedance state on the falling edge of the
last SCLK pulse. The read operation may be aborted by
bringing the CS logic input high before the data transfer is
complete. The DOUT output enters a high impedance state
on the rising edge of CS.
When an ADE7753 register is addressed for a read operation,
the entire contents of that register are transferred to the serial
port. This allows the ADE7753 to modify its on-chip
registers without the risk of corrupting data during a multi
byte transfer.
Note when a read operation follows a write operation, the
read command (i.e., write to communications register)
should not happen for at least 4µs after the end of the write
operation. If the read command is sent within 4µs of the write
operation, the last byte of the write operation may be lost.
The is given as timing specification t
9
.
Figure 54– Serial Interface Read Timing Diagram
CS
SCLK
DIN
A4 A3 A2 A1 A0
DB7
Most Significant Byte
t
1
t
2
t
3
t
4
t
5
t
8
1
DB0 DB7 DB0
t
6
Least Significant Byte
t
7
t
7
00
Command Byte
SCLK
XXXX
DB11 DB10 DB9 DB8
DIN
Most Significant Byte
DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4
Least Significant Byte
CSSCLKDIN
A4 A3 A2 A1 A0
t
1
t
11
t
11
t
9
DB7
DOUT
t
12
DB0
DB0 DB7
t
10
t
13
Most Significant Byte Least Significant Byte
000
Command Byte