Analog Devices ADE7753 A4 A3 A2 A1 A00A5

ADE7753

–33–

REV. PrC 01/02

PRELIMINARY TECHNICAL DATA

ADE7753 REGISTER DESCRIPTIONSADE7753 REGISTER DESCRIPTIONS

ADE7753 REGISTER DESCRIPTIONS

All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the

communications register and then transferring the register data. A full description of the serial interface protocol is given in

the Serial Interface section of this data sheet.

Communications RegisterCommunications Register

Communications Register

The Communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753

and the host processor. All data transfer operations must begin with a write to the communications register. The data written

to the communications register determines whether the next operation is a read or a write and which register is being accessed.

Table IV below outlines the bit designations for the Communications register.

Table V. Communications RegisterTable V. Communications Register

Table V. Communications Register

BitBit

Bit BitBit

BitBit

Bit DescriptionDescription

DescriptionDescription

Description

LocationLocation

Location MnemonicMnemonic

MnemonicMnemonic

Mnemonic

0 to 5 A0 to A5 The six LSBs of the Communications register specify the register for the data transfer

operation. Table III lists the address of each ADE7753 on-chip register.

6 RESERVED This bit is unused and should be set to zero.

7W/

RWhen this bit is a logic one the data transfer operation immediately following the write to

the Communications register will be interpreted as a write to the ADE7753. When this bit

is a logic zero the data transfer operation immediately following the write to the

Communications register will be interpreted as a read operation.

DB0

W/R

A4 A3 A2 A1 A00A5

DB1

DB2DB3

DB4DB5DB6

DB7

AddressAddress

Address NameName

NameName

Name R/WR/W

R/WR/W

R/W # of Bits# of Bits

# of Bits# of Bits

# of Bits DefaultDefault

DefaultDefault

Default DescriptionDescription

DescriptionDescription

Description

21h VPKLVL R/W 8 bits FFh Channel 2 Peak Level threshold (voltage channel). This register

sets the level of the voltage peak detection. If the channel 2 input

exceeds this level, the PKV flag in the status register is set.

22h IPEAK R 24 bits 0 h Channel 1 peak register. The maximum input value of the

Voltage channel since the last read of this register is stored in this

23h RSTIPEAK R 24 bits 0 h Same as Channel 1 peak register except that the register contents

are reset to 0 after read.

24h VPEAK R 24 bits 0h Channel 2 peak register. The maximum input value of the

Current channel since the last read of this register is stored in

this register.

25h RSTVPEAK R 24 bits 0h Same as Channel 2 peak register except that the register contents

are reset to 0 after a read.

26h TEMP R 8 bits 0h Temperature register. This is an 8-bit register which contains the

result of the latest temperature conversion – see Temperature

Measurement.

27h PERIOD R 15 bits 0 h Period of the channel 2 (volatge channel) input estimated by

Zero-crossing processing.

28h-

3Ch Reserved

3Dh TMODE R/W 8 bits Test mode register

3Eh CHKSUM R 6 bits 0h Checksum Register. This 6-bit read only register is equal to the

sum of all the ones in the previous read – see ADE7753 Serial Read

Operation.

3Fh DIEREV R 8 bits 01h Die Revision Register. This 8-bit read only register contains the

revision number of the silicon.