ADE7753
–4–REV. PrC 01/02
PRELIMINARY TECHNICAL DATA

CS

SCLK

DIN

A4 A3 A2 A1 A0 DB7
Most Significant Byte
t
1
t
2
t
3
t
4
t
5
t
8
1DB0 DB7 DB0
t
6
Least Significant Byte
t
7
t
7
00
Command Byte
CS
SCLK
DIN
A4 A3 A2 A1 A0
t
1
t
11
t
11
t
9
DB7
DOUT
t
12
DB0
DB0 DB7
t
10
t
13
Most Significant Byte Least Significant Byte
000
Command Byte
Serial Write TimingSerial Write Timing
Serial Write TimingSerial Write Timing
Serial Write Timing
Serial Read TimingSerial Read Timing
Serial Read TimingSerial Read Timing
Serial Read Timing
ADE7753 TIMING CHARACTERISTICS

1,2

Parameter A,B Versions Units Test Conditions/Comments
Write timing
t
1
20 ns (min) CS falling edge to first SCLK falling edge
t
2
150 ns (min) SCLK logic high pulse width
t
3
150 ns (min) SCLK logic low pulse width
t
4
10 ns (min) Valid Data Set up time before falling edge of SCLK
t
5
5 ns (min) Data Hold time after SCLK falling edge
t
6
TBD ns (min) Minimum time between the end of data byte transfers.
t
7
TBD ns (min) Minimum time between byte transfers during a serial write.
t
8
100 ns (min) CS Hold time after SCLK falling edge.
Read timing
t
9
TBD ns (min) Minimum time between read command (i.e. a write to Communication
Reigster) and data read.
t
10
TBD ns (min) Minimum time between data byte transfers during a multibyte read.
t
113
30 ns (min) Data access time after SCLK rising edge following a write to the
Communications Register
t
124
100 ns (max) Bus relinquish time after falling edge of SCLK.
10 ns (min)
t
134
100 ns (max) Bus relinquish time after rising edge of CS.
10 ns (min)
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)
and timed from a voltage level of 1.6V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.
4
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part
and is independent of the bus loading.
(AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)