Analog Devices ADE7753 -1

ADE7753

–26–REV. PrC 01/02

PRELIMINARY TECHNICAL DATA

51 0

APPARENT POWER

00000h

D1B71h

time (nT)

APPARENT POWER ARE

ACCUMULATED (INTEGRATED) IN

THE APPARENT ENERGY REGISTER

Apparent Power

Signal - P

51 0

VAENERGY[23:0]

VADIV

23 0

Figure 45- ADE7753 Apparent Energy calculation

The upper 52-bit of the internal register are divided by

VADIV. If the value in the VADIV register is equal to 0 then

the internal active Energy register is divided by 1. VADIV is

an 8-bit unsigned register. The upper 24-bit are then written

in the 24-bit Apparent Energy register (VAENERGY[23:0]).

RVAENERGY register (24 bits long) is provided to read the

Apparent Energy. This register is reset to zero after a read

operation.

Figure 45 shows this Apparent Energy accumulation for full

scale signals (sinusoidal) on the analog inputs. The three

curves displayed, illustrate the minimum time it takes the

energy register to roll-over when the VA Gain registers

content is equal to 7FFh, 000h and 800h. The VA Gain

the ADE7753. As shown, the fastest integration time will

occur when the VA Gain register is set to maximum full scale,

i.e., 7FFh.

40,0000h

FF,FFFFh

00,0000h

80,0000h

20,0000h

VAENERGY[23:0]

Time

(minutes)

VAGAIN = 7FFh

VAGAIN = 000h

VAGAIN = 800h

300

133 200 267

Figure 46- Energy register roll-over time for full-scale

power (Minimum & Maximum Power Gain)

Note that the Apparent Energy register contents roll-over to

full-scale negative (80,0000h) and continue increasing in

value when the power or energy flow is positive - see Figure

46.

By using the Interrupt Enable register, the ADE7754 can be

configured to issue an interrupt (IRQ) when the Apparent

Energy register is half full (positive or negative) or when an

over/under flow occurs.

Integration times under steady loadIntegration times under steady load

Integration times under steady load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.1µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

VAGAIN register set to 000h, the average word value from

Apparent Power stage is D1B71h - see Apparent Power output

range. The maximum value which can be stored in the

Apparent Energy register before it over-flows is 2

-1

FF,FFFFh. As the average word value is added to the

internal register which can store 2

- 1 or

7,FFFF,FFFF,FFFFh before it overflows, the integration

time under these conditions with VADIV=0 is calculated as

follows:

sss

hBD

FFFFhFFFFFFFF

Time 24min5231442.1

711

,,,7 ==×=

When VADIV is set to a value different from 0, the integra-

tion time varies as shown on Equation 23.

Time = Time

WDIV=0

x VADIV (23)

LINE APPARENT ENERGY ACCUMULATIONLINE APPARENT ENERGY ACCUMULATION

LINE APPARENT ENERGY ACCUMULATION

The ADE7753 is designed with a special Apparent Energy

accumulation mode which simplifies the calibration process.

By using the on-chip zero-crossing detection, the ADE7753

accumulates the Apparent Power signal in the LVAENERGY

Figure 47. The line Apparent energy accumulation mode is

always active.

The number of half line cycles is specified in the LINCYC

ADE7753 can accumulate Apparent Power for up to 65535

combined half cycles. Because the Apparent Power is inte-

grated on the same integral number of line cycles as the Line

Active Energy register, these two values can be compared

easily. The active and apparent Energy are calculated more

accurately because of this precise timing control and provide

all the information needed for Reactive Power and Power

Factor calculation. At the end of an energy calibration cycle

the LINCYC flag in the Interrupt Status register is set. If the

LINCYC mask bit in the Interrupt Mask register is enabled,

the IRQ output will also go active low. Thus the IRQ line can

also be used to signal the end of a calibration.

The Line Apparent Energy accumulation uses the same

signal path as the Apparent Energy accumulation. The LSB

size of these two registers is equivalent.

CALIBRATION

CONTROL

LINECYC[15:0]

Apparent Power

LVAENERGY REGISTER IS

UPDATED EVERY LINECYC

ZERO-CROSSINGS WITH THE

TOTAL APPARENT ENERGY

DURING THAT DURATION

LVAENERGY[23:0]

VADIV[7:0]

23 0

LPF1

FROM

CHANNEL 2

ADC

ZERO

CROSSING

DETECTION

Figure 47 - ADE7753 Apparent Energy Calibration