Analog Devices ADE7753 S

ADE7753

–18–REV. PrC 01/02

PRELIMINARY TECHNICAL DATA

V2P

V2N

ADC 2

PGA2 1

x1, x2, x4,

x8, x16

REFERENCE

GAIN[7:5]

Analog

Input Range

MULTIPLIER

-63% to + 63% FS

LPF1

0000h

4000h

C000h

2852h

D7AEh

+ FS

- FS

+ 63% FS

- 63% FS

LPF Output

word Range

WAVEFORM

2518h

DAE8h

+ 59% FS

- 59% FS

0.5V, 0.25V, 0.125V,

62.5mV, 31.25mV

2.42V

Figure 25 – ADC and Signal Processing in Channel 2

Channel 2 RMS calculationChannel 2 RMS calculation

Channel 2 RMS calculation

Figure 26 shows the details of the signal processing chain for

the RMS calculation on Channel 2. The channel 2 RMS

value is processed from the samples used in the channel 2

waveform sampling mode. The channel 2 RMS value is

stored in unsigned 24-bit registers (VRMS). 256 LSB of the

channel 2 RMS register is approximately equivalent to one

LSB of a channel 2 waveform sample. The update rate of the

channel 2 RMS measurement is CLKIN/4.

With the specified full scale AC analog input signal of 0.5V,

the LPF1 produces an output code which is approximately

62% of its full-scale value (i.e. ±10,212d) at 60 Hz- see

Channel 2 ADC. The equivalent RMS value of a full-scale AC

signal is approximately 7,221d (1C35h), which gives a

channel 2 RMS value of 1,848,772 (1C35C4h) in the VRMS

LPF3

Voltage Signal - V(t)

-63% to +63% FS

2852h

D7AEh VRMS[23:0]

175964h

00h

Channel 2

LPF1

SGN2928222120

VRMSOS[11:0]

Figure 26 - Channel 2 RMS signal processing

Channel 2 RMS offset compensationChannel 2 RMS offset compensation

Channel 2 RMS offset compensation

The ADE7753 incorporates a channel 2 RMS offset compen-

sation register (VRMSOS). This is a 12-bit signed registers

which can be used to remove offset in the channel 2 RMS

calculation. An offset may exist in the RMS calculation due

to input noises and dc offset in the input samples. The offset

calibration allows the contents of the VRMS register to be

maintained at zero when no voltage is applied.

1 LSB of the channel 2 RMS offset are equivalent to 3,600

LSB of the square of the channel 2 RMS register. Assuming

that the maximum value from the channel 2 RMS calculation

is 1,898,124d with full scale AC inputs, then 1 LSB of the

channel 2 RMS offset represents 0.05% of measurement

error at -60dB down of full scale.

3600

´+= VRMSOS

rmso

V

rms

where V

rmso

is the RMS measurement without offset correc-

tion.

PHASE COMPENSATIONPHASE COMPENSATION

PHASE COMPENSATION

When the HPF is disabled the phase error between Channel

1 and Channel 2 is zero from DC to 3.5kHz. When HPF is

enabled, Channel 1 has a phase response illustrated in

Figures 28 & 29. Also shown in Figure 30 is the magnitude

response of the filter. As can be seen from the plots, the phase

response is almost zero from 45Hz to 1kHz, This is all that

is required in typical energy measurement applications.

However, despite being internally phase compensated the

ADE7753 must work with transducers which may have

inherent phase errors. For example a phase error of 0.1° to

0.3° is not uncommon for a CT (Current Transformer).

These phase errors can vary from part to part and they must

be corrected in order to perform accurate power calculations.

The errors associated with phase mismatch are particularly

noticeable at low power factors. The ADE7753 provides a

means of digitally calibrating these small phase errors. The

ADE7753 allows a small time delay or time advance to be

introduced into the signal processing chain in order to

compensate for small phase errors. Because the compensa-

tion is in time, this technique should only be used for small

phase errors in the range of 0.1° to 0.5°. Correcting large

phase errors using a time shift technique can introduce

significant phase errors at higher harmonics.

The Phase Calibration register (PHCAL[5:0]) is a 2’s

complement signed signal byte register which has values

ranging from 21h (-31 in Decimal) to 1Fh (31 in Decimal).

By changing the PHCAL register, the time delay in the

Channel 2 signal path can change from –34.7µs to +34.7µs

(CLKIN = 3.579545MHz). One LSB is equivalent to

1.12µs time delay or advance. With a line frequency of 60Hz

this gives a phase resolution of 0.024° at the fundamental

(i.e., 360° × 1.12µs × 60Hz). Figure 27 illustrates how the

phase compensation is used to remove a 0.1° phase lead in

Channel 1 due to the external transducer. In order to cancel

the lead (0.1°) in Channel 1, a phase lead must also be

introduced into Channel 2. The resolution of the phase

adjustment allows the introduction of a phase lead in incre-

ment of 0.024°. The phase lead is achieved by introducing a

time advance into Channel 2. A time advance of 4.48µs is

made by writing -4 (3Ch) to the time delay block, thus

reducing the amount of time delay by 4.48µs, or equivalently,

a phase lead of approximately 0.1° at line frequency of 60Hz.