Analog Devices ADE7753

ADE7753

–16–REV. PrC 01/02

PRELIMINARY TECHNICAL DATA

CHANNEL 1 ADCCHANNEL 1 ADC

CHANNEL 1 ADC

Figure 21 shows the ADC and signal processing chain for

Channel 1. In waveform sampling mode the ADC outputs a

signed 2’s Complement 24-bit data word at a maximum of

27.9kSPS (CLKIN/128). The output of the ADC can be

scaled by ±50% to perform an overall power calibration or

to calibrate the ADC output. While the ADC outputs a 24-

bit 2's complement value the maximum full-scale positive

value from the ADC is limited to 400000h (+4,194,304

Decimal). The maximum full-scale negative value is limited

to C00000h (-4,194,304 Decimal). If the analog inputs are

over-ranged, the ADC output code will clamp at these values.

With the specified full scale analog input signal of 0.5V (or

0.25V or 0.125V – see Analog Inputs section) the ADC will

produce an output code which is approximately 63% of its

full-scale value. This is illustrated in Figure 21. The diagram

in Figure 21 shows a full-scale voltage signal being applied

to the differential inputs V1P and V1N. The ADC output

swings between D7AE14h (-2,642,412 Decimal) and

2851ECh (+2,642,412 Decimal). This is approximately

63% of the full-scale value 400000h. Over-ranging the

analog inputs with more than 0.5V differential (0.25 or

0.125, depending on Channel 1 full scale selection) will

cause the ADC output to increase towards its full scale value.

However, for specified operation the differential signal on the

analog inputs should not exceed the recommended value of

0.5V.

HPF

V1P

V1N

ADC 1

PGA1

x1, x2, x4,

x8, x16 REFERENCE

2.42V, 1.21V, 0.6V

Analog

Input

Range

0.5V, 0.25V,

0.125V, 62.5mV,

31.3mV, 15.6mV,

000000h

400000h

C00000h

2851ECh

D7AE14h

+ FS

- FS

+ 63% FS

- 63% FS

ADC Output

word Range

000000h

2851ECh

+ 63% FS

- 63% FS

D7AE14h

Channel 1 (Current Waveform)

Data Range

ACTIVE AND REACTIVE

POWER CALCULATION

WAVEFORM SAMPLE

Sinc3

Digital LPF

GAIN[2:0]

GAIN[4:3]

000000h

1EF73Ch

+ 48% FS

- 48% FS

E108C4h

Channel 1 (Current Waveform)

Data Range After integrator (50Hz)

DIGITAL

INTEGRATOR*

*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED

DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE

FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.

∫

000000h

19CE08h

+ 40% FS

- 40% FS

E631F8h

Channel 1 (Current Waveform)

Data Range After Integrator (60Hz)

50Hz

60Hz

CURRENT RMS (IRMS)

CALCULATION

Figure 21 —ADC and signal processing in Channel 1

Channel 1 SamplingChannel 1 Sampling

Channel 1 Sampling

The waveform samples may also be routed to the WAVE-

FORM register (MODE[14:13] = 1,0) to be read by the

system master (MCU). In waveform sampling mode the

WSMP bit (bit 3) in the Interrupt Enable register must also

be set to logic one. The Active, Apparent Power and Energy

calculation will remain uninterrupted during waveform sam-

pling.

When in waveform sample mode, one of four output sample

rates may be chosen by using bits 11 and 12 of the Mode

27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—see Mode Register.

The interrupt request output IRQ signals a new sample

availability by going active low. The timing is shown in

Figure 22. The 24-bit waveform samples are transferred

from the ADE7753 one byte (8-bits) at a time, with the most

significant byte shifted out first. The 24-bit data word is right

justified - see ADE7753 Serial Interface.

00 0 01 Hex

IRQ

DIN

DOUT

SCLK

Read from WAVEFORM

Channel 1 DATA - 24 bits

Sign

Figure 22 – Waveform sampling Channel 1

The interrupt request output IRQ stays low until the interrupt

routine reads the Reset Status register - see ADE7753 Interrupt.