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Cisco ASR 9000 Series Aggregation Services Router Overview and Reference Guide
OL-17501-09
Chapter 2 Functional Description
Fabric Controller Card
The packet diversion FPGA has three key functions:
Packet header translation between the header used by the fabric interface chip and the header
exchanged with the Ethernet interface on the route processor.
I/O interface protocol conversion (rate-matching) between the 20-Gbps DDR bus from the fabric
interface chip and the 1-Gbps interface on the processor.
Flow control to prevent overflow in the from-fabric buffer within the packet diversion FPGA, in case
of fabric congestion.
The Route Processor communicates with the switch fabric via a FIC to process control traffic. The FIC
has sufficient bandwidth to handle the control traffic and flow control in the event of fabric congestion.
External traffic is diverted to the Route Processor by the line card network processors.
The RP and FC cards in the Cisco ASR 9922 Router have control interface chips and FICs attached to
the backplanes that provide control plane and punt paths.
Fabric Controller Card
On the Cisco ASR 9922 Router and Cisco ASR 9912 Router, the switch fabric has been moved to FC
cards.
The switch fabric is configured as a single stage of switching with multiple parallel planes. The switch
fabric is responsible for transporting packets from one line card to another but has no packet processing
capabilities. Each fabric plane is a single-stage, non-blocking, packet-based, store-and-forward switch.
To manage fabric congestion, the RP provides centralized Virtual Output Queue (VOQ) arbitration.
The switch fabric is capable of delivering 550-Gbps per line card slot. When five FC cards are installed
in the chassis, the switch fabric is 4+1 redundant. When all seven FC cards are installed in the chassis,
the switch fabric is 6+1 redundant. The switch fabric is fully redundant, with one copy of the fabric on
each FC, and each FC carries enough switching capacity to meet the chassis throughput specifications.