DDR SSTL-2 Termination

SSTL-2 Termination Resistors

 

DDR

Rs

Rtt

 

 

 

 

 

MD/DQM(/DQS)

SSTL-2

 

 

 

 

 

10

33

 

 

 

 

 

MA/Control

SSTL-2

0

33

 

 

 

 

 

CS

SSTL-2

0

47

 

 

 

 

 

CKE

OD 2.5V

 

 

 

 

 

 

 

 

 

 

 

 

+1.25VS

 

 

+1.25VS

 

 

 

0402 Package

 

 

0402 Package

 

 

 

 

 

 

 

 

 

/RMD0

8

1

 

/RMA2

5

4

 

 

/RMD1

7

2

 

/RMA0

6

3

 

 

/RDQS0

6

3

 

/RMA12

7

2

 

 

/RMD2

5

4

6,7 /RSRAS#

/RSRAS#

8

1

 

 

/RMD3

RP52

8P4R-33

/RMD6

RP31

8P4R-33

 

 

8

1

 

1

8

 

 

/RMD8

7

2

 

/RDQM0

2

7

 

 

/RMD9

6

3

 

/RMD5

3

6

 

 

/RDQS1

5

4

 

/RMD4

4

5

 

 

/RMD10

RP53

8P4R-33

 

/RDQM1

RP24

8P4R-33

 

 

8

1

 

1

8

 

 

/RMD11

7

2

 

/RMD13

2

7

 

 

/RMD16

6

3

 

/RMD12

3

6

 

 

/RMD17

5

4

 

/RMD7

4

5

 

 

/RDQS2

RP54

8P4R-33

 

/RMD20

RP23

8P4R-33

 

 

8

1

 

1

8

 

 

/RMD18

7

2

 

/RMD21

2

7

 

 

/RMD19

6

3

 

/RMD15

3

6

 

 

/RMD24

5

4

 

/RMD14

4

5

 

 

/RMD25

RP55

8P4R-33

 

/RDQM2

RP22

8P4R-33

 

 

8

1

 

4

5

/RMD[0..63] /RMD[0..63]6,7

/RDQM[0..7] /RDQM[0..7]6,7

/RDQS[0..7] /RDQS[0..7]6,7

/RMA[0..14]

/RMA[0..14] 6,7

/RCS#[0..5]

/RCS#[0..5] 6,7

 

+1.25VS

DECOUPLING CAPACITOR FOR SSTL-2 END TERMIANTION VTT ISLAND

 

0603 Package placed within 200mils of VTT Termination R-packs

Schematic Diagrams

Sheet 10 of 42

DDR SSTL-2

Termination

B.Schematic

/RDQS3

7

2

/RMD22

3

6

/RMD26

6

3

/RMD23

2

7

/RMD27

5

4

/RMD28

1

8

/RMA14

RP56

8P4R-33

/RMD29

RP21

8P4R-33

8

1

4

5

/RMA9

7

2

/RDQM3

3

6

/RMA7

6

3

/RMD30

2

7

/RMA5

5

4

/RMD31

1

8

/RMA3

RP57

8P4R-33

/RMA8

RP20

8P4R-33

8

1

4

5

/RMA1

7

2

/RMA13

3

6

/RMA10

6

3

/RMA4

2

7

/RMA11

5

4

/RMA6

1

8

/RMD32

RP58

8P4R-33

/RMD37

RP17

8P4R-33

8

1

5

4

/RMD33

7

2

/RMD36

6

3

/RDQS4

6

3

/RDQM4

7

2

/RMD34

5

4

/RMD38

8

1

/RMD35

RP59

8P4R-33

/RMD44

RP30

8P4R-33

8

1

1

8

/RMD40

7

2

/RMD45

2

7

/RMD41

6

3

/RDQM5

3

6

C167 0.1UF

C203 0.1UF

C176 0.1UF

C714 0.1UF

C169 0.1UF

C715 0.1UF

C173 0.1UF

C179 0.1UF

C199 0.1UF

C207 0.1UF

C181 0.1UF

C170 0.1UF

C202 0.1UF

C175 0.1UF

C180 0.1UF

C178 0.1UF

Diagrams

/RDQS5

5

4

/RMD39

4

5

/RMD42

RP60

8P4R-33

/RMD47

RP29

8P4R-33

8

1

4

5

/RMD43

7

2

/RMD46

3

6

/RMD48

6

3

/RMD52

2

7

/RMD49

5

4

/RMD53

1

8

/RDQS6

RP61

8P4R-33

/RDQM6

RP28

8P4R-33

8

1

4

5

+1.25VS

 

 

/RMD50

7

2

/RMD54

3

6

 

 

/RMD51

6

3

/RMD55

2

7

 

 

/RMD56

5

4

/RMD60

1

8

 

 

/RMD57

RP62

8P4R-33

/RMD61

RP27

8P4R-33

 

 

8

1

4

5

 

 

/RDQS7

7

2

/RDQM7

3

6

 

 

/RMD58

6

3

/RMD62

2

7

 

 

/RMD59

5

4

/RMD63

1

8

 

 

 

RP63

8P4R-33

 

RP26

8P4R-33 +1.25VS

6,7

/RSCAS#

/RSCAS#

R189

33

/RCS#1

1

8

 

R526

33

6,7

/RSWE#

/RSWE#

/RCS#0

2

7

 

 

 

/RCS#3

3

6

 

 

 

 

 

/RCS#2

4

5

 

 

 

 

 

 

RP19

8P4R-47(0402)

 

 

 

 

 

/RCS#4

R156

47

 

 

 

 

 

/RCS#5

R155

47

C174 0.1UF

C201 0.1UF

C716 0.1UF

C722 0.1UF

C206 0.1UF

C200 0.1UF

C726 0.1UF

C727 0.1UF

C205 0.1UF

C166 0.1UF

C724 0.1UF

C721 0.1UF

C204 0.1UF

C168 0.1UF

C728 0.1UF

C725 0.1UF

DDR SSTL-2 Termination (71-D40U0-D03) B - 11

Page 87
Image 87
Clevo D480V manual DDR SSTL-2 Termination, Sheet 10, RMA0..14 6,7