Connect Tech Inc. FreeForm/Express S6 - PCIe
Hardware Description
FPGA
Description
The FreeForm/Express S6 features the Xilinx
For more details on the
http://www.xilinx.com/products/spartan6/index.htm.
PCI Express Bus
Description
The FreeForm/Express S6 has a single x1 PCIe express lane, connected directly to the
Memory & Flash
Description
A single 1024 Mbit x16 DDR3 component (Micron
In addition, a 16 Mbit SPI flash component (Numonyx M25P16) is connected to the FPGA’s user I/O for storage of embedded processor code.
Low Pin Count FMC Interface
Description
The FreeForm/Express S6 provides a single Low Pin Count FPGA Mezzanine Card (FMC) Interface. The LPC connector provides the following features
36 LVDS pairs, 2 designated as global clocks (or 68 2.5V LVCMOS pairs) I2C interface
1 SERDES TX / RX channel (Rocket I/O , GTP), with clock Power : +12VDC, +3.3V DC, +2.5V DC
The FreeForm/Express S6 LPC implementation differs from the VITA 57.1 specification as follows:
VADJ is fixed to +2.5 V DC
Only LVDS or 2.5V LVCMOS I/O is supported.
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