CY14E256L
Data Protection | Figure 4. Current Versus Cycle Time (READ) |
The CY14E256L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14E256L is in a WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
The CY14E256L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
Hardware Protect
The CY14E256L offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage condi- tions. When VCAP<VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. AutoStore can be completely disabled by tying VCC to ground and applying + 5V to VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs are only initiated by explicit request using either the software sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the CY14E256L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temper- ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14E256L depends on the following items:
■The duty cycle of chip enable
■The overall cycle rate for accesses
■The ratio of READs to WRITEs
■CMOS versus TTL input levels
■The operating temperature
■The VCC level
■IO loading
Figure 5. Current Versus Cycle Time (WRITE)
Preventing Store
The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it has to overpower the internal pull down device. This device drives HSB LOW for 20 μs at the onset of a STORE. When the CY14E256L is connected for AutoStore operation (system VCC connected to VCC and a 68 μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the CY14E256L attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and abort the STORE attempt.
Document Number: | Page 5 of 18 |
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