CY14E256L
Pin Configurations
Figure 1. Pin Diagram: 32-Pin SOIC/DIP
Pin Definitions
Pin Name | Alt | IO Type |
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| Input | Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. | ||||||||||||||
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| Input or Output | Bidirectional Data IO Lines. Used as input or output lines depending on operation. | ||||||||||||||
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| Input | Write Enable Input, Active LOW. When the chip is enabled and |
| is LOW, data on the IO | ||||
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| WE | |||||||
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| WE | W | |||||||||||||||||||
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| pins is written to the specific address location. | ||||||
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| Input | Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. | ||||||||
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| CE |
| E | |||||||||||||||||
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| Input | Output Enable, Active LOW. The active LOW |
| input enables the data output buffers during | ||||
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| OE | |||||||||
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| OE |
| G | ||||||||||||||||||
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| read cycles. Deasserting OE HIGH causes the IO pins to | ||||||
| VSS |
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| Ground | Ground for the Device. The device is connected to ground of the system. | ||||||||||||
| VCC |
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| Power Supply | Power Supply Inputs to the Device. | ||||||||||||
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| Input or Output | Hardware Store Busy | (HSB) | . When LOW, this output indicates a Hardware Store is in progress. | ||||
| HSB |
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| When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal | ||||||
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| pull up resistor keeps this pin high if not connected (connection optional). | ||||||
VCAP |
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| Power Supply | AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM | |||||||||||||
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| to nonvolatile elements. | ||||||
Document Number: | Page 2 of 18 |
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