Cypress CY62128EV30 manual Pin Configuration2, Top View, Soic

CY62128EV30

Pin Configuration[2]

A11

A9 A8

A13

WE CE2

A15

VCC

NC

A16 A14 A12

A7 A6 A5 A4

25

26

276

28

29

30

31

32

1

2

3

4

5

6

7

8

	24			A11	1		32	OE
			OE
	23		A10	A9	2		31	A10
					3
	22		CE	A8			30	CE1
	21		IO 1	A13	4		29	IO7
	20		IO7	WE	5		28	IO6
	19		IO6	CE2	6		27	IO5
STSOP	18		IO5	A15	7	TSOP I	26	IO4
Top View	17		IO4	VCC	8	Top View	25	IO3
(not to scale)	16		3	NC	9	(not to scale)	24	GND
			GND
	15		IO	A16	10		23	IO2
	14		IO2	A14	11		22	IO1
		1		A12			21	IO0
	13		IO		12
	12		A00	A7	13		20	A0
	11		A1	A6	14		19	A1
	10		A2	A5	15		18	A2
	9		A3	A4	16		17	A3

	Top View
		SOIC
NC	1	32	VCC
A16	2	31	A15
A14	3	30	CE2
A12	4	29	WE
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	25	A11
A3	9	24	OE
A2	10	23	A10
A1	11	22	CE1
A0	12	21	IO 7
IO 0	13	20	IO 6
IO 1	14	19	IO 5
IO 2	15	18	IO 4
GND	16	17	IO 3

Table 1. Product Portfolio

						Speed				Power Dissipation
Product	Range		VCC Range (V)					Operating ICC (mA)
						(ns)						Standby ISB2 (µA)
							f = 1 MHz			f = fmax
		Min		Typ[3]	Max		Typ[3]		Max	Typ[3]	Max	Typ[3]	Max
CY62128EV30LL	Ind’l/Auto-A	2.2		3.0	3.6	45	1.3		2.0	11	16	1	4
CY62128EV30LL	Auto-E	2.2		3.0	3.6	55	1.3		4.0	11	35	1	30

Notes

2.NC pins are not connected on the die.

3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

Document #: 38-05579 Rev. *D Page 2 of 11

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