Cypress CY62128EV30 manual Switching Characteristics, Read Cycle, Write Cycle

CY62128EV30

Data Retention Waveform [10]
		VCC(min)	DATA RETENTION MODE		VCC(min)
V	CC		V	> 1.5V
		tCDR	DR		tR
CE

Switching Characteristics

(Over the Operating Range)[10, 11]

Parameter		Description	45 ns (Ind’l/Auto-A)		55 ns (Auto-E)		Unit
			Min	Max	Min	Max
Read Cycle
tRC	Read Cycle Time		45		55		ns
tAA	Address to Data Valid			45		55	ns
tOHA	Data Hold from Address Change		10		10		ns
tACE		LOW to Data Valid		45		55	ns
	CE
tDOE		LOW to Data Valid		22		25	ns
	OE
tLZOE		LOW to Low Z[12]	5		5		ns
	OE
tHZOE		HIGH to High Z[12,13]		18		20	ns
	OE
t		LOW to Low Z[12]	10		10		ns
	CE
LZCE
t		HIGH to High Z[12, 13]		18		20	ns
	CE
HZCE
tPU		LOW to Power Up	0		0		ns
	CE
tPD		HIGH to Power Up		45		55	ns
	CE
Write Cycle[14]
tWC	Write Cycle Time		45		55		ns
tSCE		LOW to Write End	35		40		ns
	CE
tAW	Address Setup to Write End		35		40		ns
tHA	Address Hold from Write End		0		0		ns
tSA	Address Setup to Write Start		0		0		ns
tPWE		Pulse Width	35		40		ns
	WE
tSD	Data Setup to Write End		25		25		ns
tHD	Data Hold from Write End		0		0		ns
t		LOW to High Z[12, 13]		18		20	ns
	WE
HZWE
t		HIGH to Low Z[12]	10		10		ns
	WE
LZWE

Notes

10.CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.

11.Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.

12.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

13.tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.

14.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.

Document #: 38-05579 Rev. *D Page 5 of 11

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