CY62128EV30
Data Retention Waveform [10] |
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| VCC(min) | DATA RETENTION MODE | VCC(min) | |
V | CC | V | > 1.5V | ||
| tCDR | DR |
| tR | |
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CE |
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Switching Characteristics
(Over the Operating Range)[10, 11]
Parameter |
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| Description | 45 ns | 55 ns | Unit | ||
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| Min | Max | Min | Max | |||
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Read Cycle |
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tRC |
| Read Cycle Time | 45 |
| 55 |
| ns | |||
tAA |
| Address to Data Valid |
| 45 |
| 55 | ns | |||
tOHA |
| Data Hold from Address Change | 10 |
| 10 |
| ns | |||
tACE |
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| LOW to Data Valid |
| 45 |
| 55 | ns |
CE |
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tDOE |
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| LOW to Data Valid |
| 22 |
| 25 | ns |
OE |
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tLZOE |
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| LOW to Low Z[12] | 5 |
| 5 |
| ns |
OE |
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tHZOE |
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| HIGH to High Z[12,13] |
| 18 |
| 20 | ns |
OE |
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t |
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| LOW to Low Z[12] | 10 |
| 10 |
| ns | |
| CE |
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LZCE |
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t |
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| HIGH to High Z[12, 13] |
| 18 |
| 20 | ns | |
CE |
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HZCE |
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tPU |
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| LOW to Power Up | 0 |
| 0 |
| ns | |
| CE |
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tPD |
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| HIGH to Power Up |
| 45 |
| 55 | ns | |
CE |
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Write Cycle[14] |
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tWC |
| Write Cycle Time | 45 |
| 55 |
| ns | |||
tSCE |
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| LOW to Write End | 35 |
| 40 |
| ns | |
CE |
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tAW |
| Address Setup to Write End | 35 |
| 40 |
| ns | |||
tHA |
| Address Hold from Write End | 0 |
| 0 |
| ns | |||
tSA |
| Address Setup to Write Start | 0 |
| 0 |
| ns | |||
tPWE |
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| Pulse Width | 35 |
| 40 |
| ns |
| WE |
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tSD |
| Data Setup to Write End | 25 |
| 25 |
| ns | |||
tHD |
| Data Hold from Write End | 0 |
| 0 |
| ns | |||
t |
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| LOW to High Z[12, 13] |
| 18 |
| 20 | ns |
WE |
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HZWE |
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t |
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| HIGH to Low Z[12] | 10 |
| 10 |
| ns |
WE |
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LZWE |
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Notes
10.CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
11.Test Conditions for all parameters other than
12.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
13.tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
14.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: | Page 5 of 11 |
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