CY62128EV30
Switching Waveforms
Figure 2. Read Cycle 1 (Address transition controlled) [15, 16]
tRC
ADDRESS
tAA
tOHA
DATA OUT | PREVIOUS DATA VALID |
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| DATA VALID |
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Figure 3. Read Cycle No. 2 (OE controlled) [10, 16, 17]
ADDRESS |
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| tRC |
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CE |
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| tACE |
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OE |
| tHZOE |
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| tDOE |
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| tHZCE |
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| tLZOE | HIGH | |
| HIGH IMPEDANCE |
| IMPEDANCE |
DATA OUT | DATA VALID |
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tLZCE |
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| tPD |
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V | tPU | ICC | |
CC | 50% |
| 50% |
SUPPLY |
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CURRENT |
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| ISB |
| Figure 4. Write Cycle No. 1 (WE controlled) [10, 15, 18, 19] |
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| tWC |
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ADDRESS |
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| tSCE |
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CE |
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| tAW |
| tHA |
| tSA | tPWE |
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WE |
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OE |
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| tSD | t |
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| HD |
DATA IO | NOTE 20 | DATA VALID |
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| tHZOE |
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Notes
15.The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
16.WE is HIGH for read cycle.
17.Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
18.Data IO is high impedance if OE = VIH.
19.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
20.During this period, the IOs are in output state. Do not apply input signals.
Document #: | Page 6 of 11 |
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