Cypress CY62136EV30 CY62136EV30

CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 6 of 12

Switching Waveforms[14, 15]

Read Cycle 1 (Address Transition Controlled)[14, 15]

Read Cycle No. 2 (OE Controlled)[15, 16]

Notes:

14.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

15.WE is HIGH for read cycle.

16.Address valid prior to or coincident with CE and BHE, BLE transition LOW.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

ACE

LZBE

LZCE

DATA OUT HIGH IMPEDANCE IMPEDANCE

HZOE

HZCE

HIGH

SUPPLY

CURRENT

HZBE

BHE/BLE t

LZOE

ADDRESS

DBE

DOE

[+] Feedback

Contents

Main 2-Mbit (128K x 16) Static RAM CY62136EV30 Features Functional Description Logic Block Diagram CY62136EV30 Document #: 38-05569 Rev. *B Page 2 of 12 Pin Configuration (ns) Product VCC Range (V) Speed CY62136EV30 Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62136EV30 Document #: 38-05569 Rev. *B Page 6 of 12 Switching Waveforms Read Cycle 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[15, 16] Switching Waveforms t Document #: 38-05569 Rev. *B Page 8 of 12 Write Cycle No. 3 (WE Controlled, OE LOW)[18] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18] Truth Table Ordering Information Document #: 38-05569 Rev. *B Page 10 of 12 Package Diagrams 48-pin VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*D Package Diagrams Document History Page