Cypress CY62136EV30 Package Diagrams

CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 10 of 12

Package Diagrams

A1CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25MC A B

Ø0.05MC

0.15(4X)

0.21±0.05

1.00MAX

SEATINGPLANE

0.55MAX.

0.25C

0.10C

A1CORNER

TOPVIEW BOTTOMVIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26MAX.

48-pin VFBGA (6 x 8 x 1 mm) (51-85150)

51-85150-*D

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Contents

Main 2-Mbit (128K x 16) Static RAM CY62136EV30 Features Functional Description Logic Block Diagram CY62136EV30 Document #: 38-05569 Rev. *B Page 2 of 12 Pin Configuration (ns) Product VCC Range (V) Speed CY62136EV30 Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62136EV30 Document #: 38-05569 Rev. *B Page 6 of 12 Switching Waveforms Read Cycle 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[15, 16] Switching Waveforms t Document #: 38-05569 Rev. *B Page 8 of 12 Write Cycle No. 3 (WE Controlled, OE LOW)[18] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18] Truth Table Ordering Information Document #: 38-05569 Rev. *B Page 10 of 12 Package Diagrams 48-pin VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*D Package Diagrams Document History Page