Cypress CY62136EV30 Switching Waveforms

CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 7 of 12

Write Cycle No. 1 (WE Controlled)[13, 17, 18]

Write Cycle No. 2 (CE Controlled)[13, 17, 18]

Notes:

17.Data I/O is high impedance if OE = VIH.

18.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.

19.During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)[14, 15]

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN

NOTE19

BHE/BLE tBW

tSCE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

ADDRESS

DATA I/O

NOTE19

BHE/BLE tBW

tSA

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Contents

Main 2-Mbit (128K x 16) Static RAM CY62136EV30 Features Functional Description Logic Block Diagram CY62136EV30 Document #: 38-05569 Rev. *B Page 2 of 12 Pin Configuration (ns) Product VCC Range (V) Speed CY62136EV30 Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62136EV30 Document #: 38-05569 Rev. *B Page 6 of 12 Switching Waveforms Read Cycle 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[15, 16] Switching Waveforms t Document #: 38-05569 Rev. *B Page 8 of 12 Write Cycle No. 3 (WE Controlled, OE LOW)[18] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18] Truth Table Ordering Information Document #: 38-05569 Rev. *B Page 10 of 12 Package Diagrams 48-pin VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*D Package Diagrams Document History Page