Cypress CY62137FV30 CY62137FV30 MoBL

CY62137FV30 MoBL®

Document Number: 001-07141 Rev. *F Page 7 of 12

Figure 7. Write Cycle 1: WE Controlled [16, 20, 21]

Figure 8. Write Cycle 2: CE Controlled [16, 20, 21]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

tHZOE

DATAIN

NOTE 22

tBW

tSCE

DATA IO

ADDRESS

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

tBW

tSA

ADDRESS

DATA IO

BHE/BLE

NOTE 22

Notes

20.Data IO is high impedance if OE = VIH.

21.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.

22.During this period, the IOs are in output state. Do not apply input signals.

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Contents

Main CY62137FV30 MoBL 2-Mbit (128K x 16) Static RAM Features Functional Description Logic Block Diagram CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 2 of 12 Product Portfolio Product Range VCC Range (V) Speed (ns) Pin Configuration CY62137FV30 MoBL Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 6 of 12 PREVIOUS DATA VALID DATA VALID Switching Waveforms Figure 5. Read Cycle 1: Address Transition Controlled [17, 18] CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 7 of 12 Figure 7. Write Cycle 1: WE Controlled [16, 20, 21] t Figure 8. Write Cycle 2: CE Controlled [16, 20, 21] Document Number: 001-07141 Rev. *F Page 8 of 12 Figure 9. Write Cycle 3: WE Controlled, OE LOW [21] Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [21] Truth Table Document Number: 001-07141 Rev. *F Page 10 of 12 Ordering Information Diagram Package Type Operating Speed (ns) Ordering Code Package Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) 51-85150-*D Page Document History Page